Re: [PATCH 1/2] drm/i915: move intel_hrawclk() to intel_display.c

[Jani Nikula <jani.nikula@intel.com>]

On Tue, 07 Jan 2014, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, Jan 07, 2014 at 06:01:33PM +0200, Jani Nikula wrote:
>> Make it available outside of intel_dp.c.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Since this only really applies to gmch platforms I wonder whether we
> should give this a more platforms specific prefix. Established precedence
> would point towardy i9xx_ I think ... But I'm happy with other colors,
> too. Maybe a patch on top of this series for less fuzz?

Good point, will do (once we have this cleared up).

BR,
Jani.

> -Daniel
>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c |   33 +++++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/i915/intel_dp.c      |   34 ----------------------------------
>>  drivers/gpu/drm/i915/intel_drv.h     |    1 +
>>  3 files changed, 34 insertions(+), 34 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index a562eef..e784feb 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -78,6 +78,39 @@ intel_pch_rawclk(struct drm_device *dev)
>>  	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
>>  }
>>  
>> +/* hrawclock is 1/4 the FSB frequency */
>> +int intel_hrawclk(struct drm_device *dev)
>> +{
>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>> +	uint32_t clkcfg;
>> +
>> +	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
>> +	if (IS_VALLEYVIEW(dev))
>> +		return 200;
>> +
>> +	clkcfg = I915_READ(CLKCFG);
>> +	switch (clkcfg & CLKCFG_FSB_MASK) {
>> +	case CLKCFG_FSB_400:
>> +		return 100;
>> +	case CLKCFG_FSB_533:
>> +		return 133;
>> +	case CLKCFG_FSB_667:
>> +		return 166;
>> +	case CLKCFG_FSB_800:
>> +		return 200;
>> +	case CLKCFG_FSB_1067:
>> +		return 266;
>> +	case CLKCFG_FSB_1333:
>> +		return 333;
>> +	/* these two are just a guess; one of them might be right */
>> +	case CLKCFG_FSB_1600:
>> +	case CLKCFG_FSB_1600_ALT:
>> +		return 400;
>> +	default:
>> +		return 133;
>> +	}
>> +}
>> +
>>  static inline u32 /* units of 100MHz */
>>  intel_fdi_link_freq(struct drm_device *dev)
>>  {
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 7df5085..a36a2a3 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -203,40 +203,6 @@ unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
>>  		dst[i] = src >> ((3-i) * 8);
>>  }
>>  
>> -/* hrawclock is 1/4 the FSB frequency */
>> -static int
>> -intel_hrawclk(struct drm_device *dev)
>> -{
>> -	struct drm_i915_private *dev_priv = dev->dev_private;
>> -	uint32_t clkcfg;
>> -
>> -	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
>> -	if (IS_VALLEYVIEW(dev))
>> -		return 200;
>> -
>> -	clkcfg = I915_READ(CLKCFG);
>> -	switch (clkcfg & CLKCFG_FSB_MASK) {
>> -	case CLKCFG_FSB_400:
>> -		return 100;
>> -	case CLKCFG_FSB_533:
>> -		return 133;
>> -	case CLKCFG_FSB_667:
>> -		return 166;
>> -	case CLKCFG_FSB_800:
>> -		return 200;
>> -	case CLKCFG_FSB_1067:
>> -		return 266;
>> -	case CLKCFG_FSB_1333:
>> -		return 333;
>> -	/* these two are just a guess; one of them might be right */
>> -	case CLKCFG_FSB_1600:
>> -	case CLKCFG_FSB_1600_ALT:
>> -		return 400;
>> -	default:
>> -		return 133;
>> -	}
>> -}
>> -
>>  static void
>>  intel_dp_init_panel_power_sequencer(struct drm_device *dev,
>>  				    struct intel_dp *intel_dp,
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 46aea6c..9c5e984 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -626,6 +626,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>>  
>>  /* intel_display.c */
>>  int intel_pch_rawclk(struct drm_device *dev);
>> +int intel_hrawclk(struct drm_device *dev);
>>  void intel_mark_busy(struct drm_device *dev);
>>  void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
>>  			struct intel_ring_buffer *ring);
>> -- 
>> 1.7.10.4
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center