From mboxrd@z Thu Jan  1 00:00:00 1970
From: Eric Anholt <eric@anholt.net>
Subject: Re: [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing
	on gen6+.
Date: Wed, 05 Oct 2011 17:59:31 -0700
Message-ID: <87zkhf2avg.fsf@eliezer.anholt.net>
References: <1317708160-1761-1-git-send-email-kenneth@whitecape.org>
	<1317708160-1761-3-git-send-email-kenneth@whitecape.org>
	<20111005155713.6e2f0c6c@bwidawsk.net>
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On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> I think we also want a TLB invalidate here, bit 18.  This requires another
> workaround before issuing this flush: We need 2 Store Data Commands (such=
 as
> MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) before sending PIPE_CONTROL w/ =
stall
> (20) and TLB inv bit (18) set

From=20the docs for GFX_MODE:

    "This field controls the invalidation if the TLB cache inside the
     hardware. When enabled this bit limits the invalidation of the TLB
     only to batch buffer boundaries or to pipe_control commands which
     have the TLB invalidation bit set. If disabled, the TLB caches are
     flushed for every full flush of the pipeline"

We're already getting TLB invalidate at batchbuffer boundaries
(actually, even more: every pipeline stall, since that bit is 0 on my
hardware).  What would we need this new flush for?

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