From: shuang.he@intel.com
To: shuang.he@intel.com, intel-gfx@lists.freedesktop.org,
damien.lespiau@intel.com
Subject: Re: [PATCH 10/10] drm/i915/skl: Apply eDP WA only for gen <
Date: 13 Nov 2014 16:39:33 -0800 [thread overview]
Message-ID: <898e4a$ccv8vi@FMSMGA003.fm.intel.com> (raw)
In-Reply-To: <1415890522-31856-11-git-send-email-damien.lespiau@intel.com>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=291/291->290/291
PNV: pass/total=356/356->355/356
ILK: pass/total=372/372->371/372
IVB: pass/total=544/546->545/546
SNB: pass/total=423/425->424/425
HSW: pass/total=579/579->579/579
BDW: pass/total=433/435->434/435
-------------------------------------Detailed-------------------------------------
test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)...
BYT: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(15, M36M31)PASS(1, M38) -> TIMEOUT(4, M36)
PNV: Intel_gpu_tools, igt_gen3_mixed_blits, CRASH(1, M23)NRUN(2, M23)PASS(4, M25M7) -> CRASH(1, M7)PASS(3, M7)
ILK: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, FAIL(3, M26)DMESG_FAIL(1, M26)TIMEOUT(25, M37M6M26)PASS(1, M26) -> TIMEOUT(4, M6)
IVB: Intel_gpu_tools, igt_gem_bad_reloc_negative-reloc, NSPT(5, M4M21M34M45)PASS(8, M21M34M4M45) -> NSPT(1, M4)PASS(3, M4)
SNB: Intel_gpu_tools, igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked, FAIL(1, M22)PASS(9, M35M22) -> PASS(4, M22)
BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, DMESG_WARN(1, M30)PASS(9, M30M42) -> PASS(4, M30)
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next prev parent reply other threads:[~2014-11-14 0:48 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-13 14:55 [PATCH 00/10] SKL stage 1 part 3 Damien Lespiau
2014-11-13 14:55 ` [PATCH 01/10] drm/i915/skl: Register definitions for SKL Clocks Damien Lespiau
2014-11-13 14:55 ` [PATCH 02/10] drm/i915/skl: Structure/enum definitions for SKL clocks Damien Lespiau
2014-11-13 14:55 ` [PATCH 03/10] drm/i915/skl: CD clock back calculation for SKL Damien Lespiau
2014-11-13 14:55 ` [PATCH 04/10] drm/i915/skl: Determine enabled PLL and its linkrate/pixel clock Damien Lespiau
2014-11-13 14:55 ` [PATCH 05/10] drm/i915/skl: Query DPLL attached to port on SKL Damien Lespiau
2014-11-13 14:55 ` [PATCH 06/10] drm/i915/skl: Define shared DPLLs for Skylake Damien Lespiau
2014-11-13 14:55 ` [PATCH 07/10] drm/i915/skl: Adjust the port PLL selection code Damien Lespiau
2014-11-13 14:55 ` [PATCH 08/10] drm/i915/skl: Implementation of SKL DPLL programming Damien Lespiau
2014-11-13 14:55 ` [PATCH 09/10] drm/i915/skl: Provide skl-specific pll hw state cross-checking Damien Lespiau
2014-11-13 14:55 ` [PATCH 10/10] drm/i915/skl: Apply eDP WA only for gen < 9 Damien Lespiau
2014-11-14 0:39 ` shuang.he [this message]
2014-11-14 10:20 ` [PATCH 00/10] SKL stage 1 part 3 Daniel Vetter
2014-11-14 11:30 ` Damien Lespiau
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