* [PATCH v3 1/2] drm/i915: move RPS PM_IER enabling to gen6_enable_rps_interrupts
@ 2014-12-15 16:59 Imre Deak
2014-12-15 16:59 ` [PATCH v3 2/2] drm/i915: sanitize RPS resetting during GPU reset Imre Deak
0 siblings, 1 reply; 4+ messages in thread
From: Imre Deak @ 2014-12-15 16:59 UTC (permalink / raw)
To: intel-gfx, Jani Nikula
Paulo noticed that we don't enable RPS interrupts via PM_IER in
gen6_enable_rps_interrupts(). This wasn't a problem so far, since the
only place we disabled RPS interrupts was during system/runtime suspend
and after that we reenable all interrupts in the IRQ pre/postinstall
hooks.
In the next patch we'll disable/reenable RPS interrupts during GPU reset
too, but not call IRQ uninstall, pre/postinstall hooks, so there the
above wouldn't work. The logical place for programming PM_IER is
gen6_enable_rps_interrupts() and this also makes the function more
symmetric with gen6_disable_rps_interrupts(), so move the programming
there from the postinstall hooks.
Note that these changes don't affect the ILK RPS interrupt code, which
could be sanitized in a similar way. But that can be done as a
follow-up.
Credits-to: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
[Jani, the patchset only applies on top of
"i915: mask RPS IRQs properly when disabling RPS"]
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8bab2ab..996c293 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -281,10 +281,14 @@ void gen6_enable_rps_interrupts(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
spin_lock_irq(&dev_priv->irq_lock);
+
WARN_ON(dev_priv->rps.pm_iir);
WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
dev_priv->rps.interrupts_enabled = true;
+ I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
+ dev_priv->pm_rps_events);
gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
+
spin_unlock_irq(&dev_priv->irq_lock);
}
@@ -3307,8 +3311,10 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
if (INTEL_INFO(dev)->gen >= 6) {
- pm_irqs |= dev_priv->pm_rps_events;
-
+ /*
+ * RPS interrupts will get enabled/disabled on demand when RPS
+ * itself is enabled/disabled.
+ */
if (HAS_VEBOX(dev))
pm_irqs |= PM_VEBOX_USER_INTERRUPT;
@@ -3520,7 +3526,11 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
dev_priv->pm_irq_mask = 0xffffffff;
GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
- GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events);
+ /*
+ * RPS interrupts will get enabled/disabled on demand when RPS itself
+ * is enabled/disabled.
+ */
+ GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
}
--
1.8.4
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^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v3 2/2] drm/i915: sanitize RPS resetting during GPU reset
2014-12-15 16:59 [PATCH v3 1/2] drm/i915: move RPS PM_IER enabling to gen6_enable_rps_interrupts Imre Deak
@ 2014-12-15 16:59 ` Imre Deak
2014-12-15 17:15 ` Jani Nikula
2014-12-15 23:58 ` shuang.he
0 siblings, 2 replies; 4+ messages in thread
From: Imre Deak @ 2014-12-15 16:59 UTC (permalink / raw)
To: intel-gfx, Jani Nikula
Atm, we don't disable RPS interrupts and related work items before
resetting the GPU. This may interfere with the following GPU
initialization and cause RPS interrupts to show up in PM_IIR too early
before calling gen6_enable_rps_interrupts() (triggering a WARN there).
Solve this by disabling RPS interrupts and flushing any related work
items before resetting the GPU.
v2:
- split out the common parts of the gt suspend and the new gt reset
functions (Paulo)
v3:
- remove the check for UMS, it's a NOP nowadays (Daniel)
Reported-by: He, Shuang <shuang.he@intel.com>
Testcase: igt/gem_reset_stats/ban-render
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86644
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 +++-
drivers/gpu/drm/i915/intel_pm.c | 28 +++++++++++++++++++---------
2 files changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f990ab4..fc8cfdd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -811,6 +811,8 @@ int i915_reset(struct drm_device *dev)
if (!i915.reset)
return 0;
+ intel_reset_gt_powersave(dev);
+
mutex_lock(&dev->struct_mutex);
i915_gem_reset(dev);
@@ -880,7 +882,7 @@ int i915_reset(struct drm_device *dev)
* of re-init after reset.
*/
if (INTEL_INFO(dev)->gen > 5)
- intel_reset_gt_powersave(dev);
+ intel_enable_gt_powersave(dev);
} else {
mutex_unlock(&dev->struct_mutex);
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1f4b56e..964b28e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6191,6 +6191,20 @@ void intel_cleanup_gt_powersave(struct drm_device *dev)
valleyview_cleanup_gt_powersave(dev);
}
+static void gen6_suspend_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ flush_delayed_work(&dev_priv->rps.delayed_resume_work);
+
+ /*
+ * TODO: disable RPS interrupts on GEN9+ too once RPS support
+ * is added for it.
+ */
+ if (INTEL_INFO(dev)->gen < 9)
+ gen6_disable_rps_interrupts(dev);
+}
+
/**
* intel_suspend_gt_powersave - suspend PM work and helper threads
* @dev: drm device
@@ -6206,14 +6220,7 @@ void intel_suspend_gt_powersave(struct drm_device *dev)
if (INTEL_INFO(dev)->gen < 6)
return;
- flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
- /*
- * TODO: disable RPS interrupts on GEN9+ too once RPS support
- * is added for it.
- */
- if (INTEL_INFO(dev)->gen < 9)
- gen6_disable_rps_interrupts(dev);
+ gen6_suspend_rps(dev);
/* Force GPU to min freq during suspend */
gen6_rps_idle(dev_priv);
@@ -6316,8 +6323,11 @@ void intel_reset_gt_powersave(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ if (INTEL_INFO(dev)->gen < 6)
+ return;
+
+ gen6_suspend_rps(dev);
dev_priv->rps.enabled = false;
- intel_enable_gt_powersave(dev);
}
static void ibx_init_clock_gating(struct drm_device *dev)
--
1.8.4
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^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH v3 2/2] drm/i915: sanitize RPS resetting during GPU reset
2014-12-15 16:59 ` [PATCH v3 2/2] drm/i915: sanitize RPS resetting during GPU reset Imre Deak
@ 2014-12-15 17:15 ` Jani Nikula
2014-12-15 23:58 ` shuang.he
1 sibling, 0 replies; 4+ messages in thread
From: Jani Nikula @ 2014-12-15 17:15 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On Mon, 15 Dec 2014, Imre Deak <imre.deak@intel.com> wrote:
> Atm, we don't disable RPS interrupts and related work items before
> resetting the GPU. This may interfere with the following GPU
> initialization and cause RPS interrupts to show up in PM_IIR too early
> before calling gen6_enable_rps_interrupts() (triggering a WARN there).
>
> Solve this by disabling RPS interrupts and flushing any related work
> items before resetting the GPU.
>
> v2:
> - split out the common parts of the gt suspend and the new gt reset
> functions (Paulo)
> v3:
> - remove the check for UMS, it's a NOP nowadays (Daniel)
>
> Reported-by: He, Shuang <shuang.he@intel.com>
> Testcase: igt/gem_reset_stats/ban-render
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86644
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Pushed both to drm-intel-next-fixes, thanks for the patches and review.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 +++-
> drivers/gpu/drm/i915/intel_pm.c | 28 +++++++++++++++++++---------
> 2 files changed, 22 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index f990ab4..fc8cfdd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -811,6 +811,8 @@ int i915_reset(struct drm_device *dev)
> if (!i915.reset)
> return 0;
>
> + intel_reset_gt_powersave(dev);
> +
> mutex_lock(&dev->struct_mutex);
>
> i915_gem_reset(dev);
> @@ -880,7 +882,7 @@ int i915_reset(struct drm_device *dev)
> * of re-init after reset.
> */
> if (INTEL_INFO(dev)->gen > 5)
> - intel_reset_gt_powersave(dev);
> + intel_enable_gt_powersave(dev);
> } else {
> mutex_unlock(&dev->struct_mutex);
> }
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1f4b56e..964b28e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6191,6 +6191,20 @@ void intel_cleanup_gt_powersave(struct drm_device *dev)
> valleyview_cleanup_gt_powersave(dev);
> }
>
> +static void gen6_suspend_rps(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + flush_delayed_work(&dev_priv->rps.delayed_resume_work);
> +
> + /*
> + * TODO: disable RPS interrupts on GEN9+ too once RPS support
> + * is added for it.
> + */
> + if (INTEL_INFO(dev)->gen < 9)
> + gen6_disable_rps_interrupts(dev);
> +}
> +
> /**
> * intel_suspend_gt_powersave - suspend PM work and helper threads
> * @dev: drm device
> @@ -6206,14 +6220,7 @@ void intel_suspend_gt_powersave(struct drm_device *dev)
> if (INTEL_INFO(dev)->gen < 6)
> return;
>
> - flush_delayed_work(&dev_priv->rps.delayed_resume_work);
> -
> - /*
> - * TODO: disable RPS interrupts on GEN9+ too once RPS support
> - * is added for it.
> - */
> - if (INTEL_INFO(dev)->gen < 9)
> - gen6_disable_rps_interrupts(dev);
> + gen6_suspend_rps(dev);
>
> /* Force GPU to min freq during suspend */
> gen6_rps_idle(dev_priv);
> @@ -6316,8 +6323,11 @@ void intel_reset_gt_powersave(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + if (INTEL_INFO(dev)->gen < 6)
> + return;
> +
> + gen6_suspend_rps(dev);
> dev_priv->rps.enabled = false;
> - intel_enable_gt_powersave(dev);
> }
>
> static void ibx_init_clock_gating(struct drm_device *dev)
> --
> 1.8.4
>
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v3 2/2] drm/i915: sanitize RPS resetting during GPU reset
2014-12-15 16:59 ` [PATCH v3 2/2] drm/i915: sanitize RPS resetting during GPU reset Imre Deak
2014-12-15 17:15 ` Jani Nikula
@ 2014-12-15 23:58 ` shuang.he
1 sibling, 0 replies; 4+ messages in thread
From: shuang.he @ 2014-12-15 23:58 UTC (permalink / raw)
To: shuang.he, intel-gfx, imre.deak
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 364/364 364/364
ILK +5-2 360/366 363/366
SNB 448/450 448/450
IVB 497/498 497/498
BYT 289/289 289/289
HSW 563/564 563/564
BDW 417/417 417/417
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
ILK igt_kms_flip_rcs-flip-vs-panning-interruptible DMESG_WARN(1, M26)PASS(1, M26) DMESG_WARN(1, M26)
ILK igt_drv_suspend_fence-restore-untiled DMESG_WARN(1, M26)PASS(5, M37M26) PASS(1, M26)
ILK igt_kms_flip_bcs-flip-vs-modeset-interruptible DMESG_WARN(1, M26)PASS(5, M37M26) PASS(1, M26)
ILK igt_kms_flip_busy-flip-interruptible DMESG_WARN(1, M26)PASS(5, M37M26) PASS(1, M26)
*ILK igt_kms_flip_flip-vs-panning PASS(2, M26) NSPT(1, M26)
ILK igt_kms_flip_flip-vs-rmfb-interruptible DMESG_WARN(1, M26)PASS(5, M37M26) PASS(1, M26)
ILK igt_kms_flip_rcs-flip-vs-dpms DMESG_WARN(1, M26)PASS(4, M37M26) PASS(1, M26)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2014-12-15 16:59 [PATCH v3 1/2] drm/i915: move RPS PM_IER enabling to gen6_enable_rps_interrupts Imre Deak
2014-12-15 16:59 ` [PATCH v3 2/2] drm/i915: sanitize RPS resetting during GPU reset Imre Deak
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2014-12-15 23:58 ` shuang.he
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