* [PATCH v2] drm/i915: FIFO space query code refactor @ 2014-12-18 16:45 Dave Gordon 2014-12-19 10:11 ` shuang.he 0 siblings, 1 reply; 6+ messages in thread From: Dave Gordon @ 2014-12-18 16:45 UTC (permalink / raw) To: intel-gfx When querying the GTFIFOCTL register to check the FIFO space, the read value must be masked. The operation is repeated explicitly in several places. This change refactors the read-and-mask code into a function call. v2: rebase to latest drm-intel-nightly Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef Signed-off-by: Dave Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index e9561de..d29b4d4 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -147,6 +147,13 @@ static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, gen6_gt_check_fifodbg(dev_priv); } +static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) +{ + u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); + + return count & GT_FIFO_FREE_ENTRIES_MASK; +} + static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) { int ret = 0; @@ -154,16 +161,15 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) /* On VLV, FIFO will be shared by both SW and HW. * So, we need to read the FREE_ENTRIES everytime */ if (IS_VALLEYVIEW(dev_priv->dev)) - dev_priv->uncore.fifo_count = - __raw_i915_read32(dev_priv, GTFIFOCTL) & - GT_FIFO_FREE_ENTRIES_MASK; + dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { int loop = 500; - u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; + u32 fifo = fifo_free_entries(dev_priv); + while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { udelay(10); - fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; + fifo = fifo_free_entries(dev_priv); } if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) ++ret; @@ -505,8 +511,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) if (IS_GEN6(dev) || IS_GEN7(dev)) dev_priv->uncore.fifo_count = - __raw_i915_read32(dev_priv, GTFIFOCTL) & - GT_FIFO_FREE_ENTRIES_MASK; + fifo_free_entries(dev_priv); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915: FIFO space query code refactor 2014-12-18 16:45 [PATCH v2] drm/i915: FIFO space query code refactor Dave Gordon @ 2014-12-19 10:11 ` shuang.he 0 siblings, 0 replies; 6+ messages in thread From: shuang.he @ 2014-12-19 10:11 UTC (permalink / raw) To: shuang.he, intel-gfx, david.s.gordon Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) -------------------------------------Summary------------------------------------- Platform Delta drm-intel-nightly Series Applied PNV -1 364/364 363/364 ILK -7 364/366 357/366 SNB -1 448/450 447/450 IVB -1 497/498 496/498 BYT -1 289/289 288/289 HSW -1 563/564 562/564 BDW -1 416/417 415/417 -------------------------------------Detailed------------------------------------- Platform Test drm-intel-nightly Series Applied PNV igt_gem_exec_blt NRUN(5, M23M7M25)PASS(1, M25) NRUN(1, M23) ILK igt_gem_exec_blt NRUN(7, M37M26)PASS(1, M26) NRUN(1, M26) ILK igt_kms_render_direct-render DMESG_WARN(1, M26)PASS(3, M26) DMESG_WARN(1, M26) ILK igt_kms_flip_blocking-absolute-wf_vblank-interruptible DMESG_WARN(1, M26)PASS(2, M26) DMESG_WARN(1, M26) *ILK igt_kms_flip_plain-flip-fb-recreate-interruptible PASS(3, M26) DMESG_WARN(1, M26) *ILK igt_kms_flip_rcs-flip-vs-dpms NSPT(1, M26)PASS(3, M26) DMESG_WARN(1, M26) *ILK igt_kms_flip_vblank-vs-hang PASS(3, M26) NSPT(1, M26) *ILK igt_kms_flip_wf_vblank-ts-check PASS(4, M26) DMESG_WARN(1, M26) SNB igt_gem_exec_blt NRUN(7, M35M22)PASS(1, M35) NRUN(1, M35) IVB igt_gem_exec_blt NRUN(7, M34M21M4)PASS(1, M34) NRUN(1, M21) BYT igt_gem_exec_blt NRUN(7, M48M49M50M51)PASS(1, M48) NRUN(1, M49) HSW igt_gem_exec_blt NRUN(7, M40M20M19)PASS(1, M40) NRUN(1, M19) BDW igt_gem_exec_blt NRUN(6, M30M28)PASS(1, M28) NRUN(1, M28) Note: You need to pay more attention to line start with '*' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2*] drm/i915: FIFO space query code refactor @ 2014-12-18 16:48 Dave Gordon 0 siblings, 0 replies; 6+ messages in thread From: Dave Gordon @ 2014-12-18 16:48 UTC (permalink / raw) To: intel-gfx When querying the GTFIFOCTL register to check the FIFO space, the read value must be masked. The operation is repeated explicitly in several places. This change refactors the read-and-mask code into a function call. v2*: rebased on top of Mika's forcewake changes Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef Signed-off-by: Dave Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 5e2b11f..fc3bcf5 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -205,6 +205,13 @@ static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, gen6_gt_check_fifodbg(dev_priv); } +static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) +{ + u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); + + return count & GT_FIFO_FREE_ENTRIES_MASK; +} + static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) { int ret = 0; @@ -212,16 +219,15 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) /* On VLV, FIFO will be shared by both SW and HW. * So, we need to read the FREE_ENTRIES everytime */ if (IS_VALLEYVIEW(dev_priv->dev)) - dev_priv->uncore.fifo_count = - __raw_i915_read32(dev_priv, GTFIFOCTL) & - GT_FIFO_FREE_ENTRIES_MASK; + dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { int loop = 500; - u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; + u32 fifo = fifo_free_entries(dev_priv); + while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { udelay(10); - fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; + fifo = fifo_free_entries(dev_priv); } if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) ++ret; @@ -277,8 +283,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) if (IS_GEN6(dev) || IS_GEN7(dev)) dev_priv->uncore.fifo_count = - __raw_i915_read32(dev_priv, GTFIFOCTL) & - GT_FIFO_FREE_ENTRIES_MASK; + fifo_free_entries(dev_priv); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 00/10] Prep work patches for GPU scheduler @ 2014-12-09 12:59 John.C.Harrison 2014-12-09 12:59 ` [PATCH 04/10] drm/i915: FIFO space query code refactor John.C.Harrison 0 siblings, 1 reply; 6+ messages in thread From: John.C.Harrison @ 2014-12-09 12:59 UTC (permalink / raw) To: Intel-GFX From: John Harrison <John.C.Harrison@Intel.com> Assorted patches to make the tree more friendly to the GPU scheduler. The biggest change is to re-organise the execbuff code path. Basically, the scheduler needs to split the submission path into two sections which are essentially software only (data structure creation, manipulation, etc.) and hardware only (actually writing the commands to the write / execlist). As this is not a small change, any other changes to the execution code path tend to cause merge conflicts and other such headaches for the scheduler. Thus it would be extremely useful to get this preparation work committed to the tree while the scheduler is still being re-worked for upstream acceptability. The other patches in the series are various minor fixes that were spotted along the way to getting the scheduler working. [Patches against drm-intel-nightly tree fetched 08/12/2014] Dave Gordon (3): drm/i915: Updating assorted register and status page definitions drm/i915: FIFO space query code refactor drm/i915: Disable 'get seqno' workaround for VLV John Harrison (7): drm/i915: Rename 'flags' to 'dispatch_flags' for better code reading drm/i915: Add missing trace point to LRC execbuff code path drm/i915: Add extra add_request calls drm/i915: Early alloc request drm/i915: Prelude to splitting i915_gem_do_execbuffer in two drm/i915: Split i915_dem_do_execbuffer() in half drm/i915: Cache ringbuf pointer in request structure drivers/gpu/drm/i915/i915_drv.h | 53 ++++-- drivers/gpu/drm/i915/i915_gem.c | 63 +++---- drivers/gpu/drm/i915/i915_gem_context.c | 9 + drivers/gpu/drm/i915/i915_gem_execbuffer.c | 237 +++++++++++++++++--------- drivers/gpu/drm/i915/i915_gem_gtt.c | 9 + drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 30 +++- drivers/gpu/drm/i915/intel_display.c | 23 ++- drivers/gpu/drm/i915/intel_lrc.c | 102 +++++++---- drivers/gpu/drm/i915/intel_lrc.h | 12 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 12 +- drivers/gpu/drm/i915/intel_ringbuffer.h | 44 ++++- drivers/gpu/drm/i915/intel_uncore.c | 19 ++- 13 files changed, 426 insertions(+), 189 deletions(-) -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 04/10] drm/i915: FIFO space query code refactor 2014-12-09 12:59 [PATCH 00/10] Prep work patches for GPU scheduler John.C.Harrison @ 2014-12-09 12:59 ` John.C.Harrison 2014-12-09 13:32 ` [PATCH 8/8] drm/i915: Enum forcewake domains and domain identifiers Jani Nikula 0 siblings, 1 reply; 6+ messages in thread From: John.C.Harrison @ 2014-12-09 12:59 UTC (permalink / raw) To: Intel-GFX From: Dave Gordon <david.s.gordon@intel.com> When querying the GTFIFOCTL register to check the FIFO space, the read value must be masked. The operation is repeated explicitly in several places. This change refactors the read-and-mask code into a function call. Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef Signed-off-by: Dave Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 46de8d7..4021831 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -47,6 +47,13 @@ assert_device_not_suspended(struct drm_i915_private *dev_priv) "Device suspended\n"); } +static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) +{ + u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); + + return count & GT_FIFO_FREE_ENTRIES_MASK; +} + static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) { /* w/a for a sporadic read returning 0 by waiting for the GT @@ -154,16 +161,15 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) /* On VLV, FIFO will be shared by both SW and HW. * So, we need to read the FREE_ENTRIES everytime */ if (IS_VALLEYVIEW(dev_priv->dev)) - dev_priv->uncore.fifo_count = - __raw_i915_read32(dev_priv, GTFIFOCTL) & - GT_FIFO_FREE_ENTRIES_MASK; + dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { int loop = 500; - u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; + u32 fifo = fifo_free_entries(dev_priv); + while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { udelay(10); - fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; + fifo = fifo_free_entries(dev_priv); } if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) ++ret; @@ -505,8 +511,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) if (IS_GEN6(dev) || IS_GEN7(dev)) dev_priv->uncore.fifo_count = - __raw_i915_read32(dev_priv, GTFIFOCTL) & - GT_FIFO_FREE_ENTRIES_MASK; + fifo_free_entries(dev_priv); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 8/8] drm/i915: Enum forcewake domains and domain identifiers @ 2014-12-09 13:32 ` Jani Nikula 2014-12-10 10:41 ` [PATCH 04/10] drm/i915: FIFO space query code refactor Daniel Vetter 0 siblings, 1 reply; 6+ messages in thread From: Jani Nikula @ 2014-12-09 13:32 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx; +Cc: daniel.vetter On Tue, 09 Dec 2014, Mika Kuoppala <mika.kuoppala@linux.intel.com> wrote: > Make the domains and domain identifiers enums. To emphasize > the difference in order to avoid mistakes. > > Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch> > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 41 +++++++++++++++++---------------- > drivers/gpu/drm/i915/intel_uncore.c | 45 +++++++++++++++++++------------------ > 2 files changed, 45 insertions(+), 41 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 0d47397..5c6c372 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -533,11 +533,28 @@ struct drm_i915_display_funcs { > void (*enable_backlight)(struct intel_connector *connector); > }; > > +enum fw_domain_id { Does anyone else think of "firmware" first when seeing "fw", and "forcewake" only after a moment? Jani. > + FW_DOMAIN_ID_RENDER = 0, > + FW_DOMAIN_ID_BLITTER, > + FW_DOMAIN_ID_MEDIA, > + > + FW_DOMAIN_ID_COUNT > +}; > + > +enum fw_domains { > + FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), > + FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), > + FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), > + FORCEWAKE_ALL = (FORCEWAKE_RENDER | > + FORCEWAKE_BLITTER | > + FORCEWAKE_MEDIA) > +}; > + > struct intel_uncore_funcs { > void (*force_wake_get)(struct drm_i915_private *dev_priv, > - int fw_engine); > + enum fw_domains domains); > void (*force_wake_put)(struct drm_i915_private *dev_priv, > - int fw_engine); > + enum fw_domains domains); > > uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); > uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); > @@ -554,25 +571,17 @@ struct intel_uncore_funcs { > uint64_t val, bool trace); > }; > > -enum { > - FW_DOMAIN_ID_RENDER = 0, > - FW_DOMAIN_ID_BLITTER, > - FW_DOMAIN_ID_MEDIA, > - > - FW_DOMAIN_ID_COUNT > -}; > - > struct intel_uncore { > spinlock_t lock; /** lock is also taken in irq contexts. */ > > struct intel_uncore_funcs funcs; > > unsigned fifo_count; > - unsigned fw_domains; > + enum fw_domains fw_domains; > > struct intel_uncore_forcewake_domain { > struct drm_i915_private *i915; > - int id; > + enum fw_domain_id id; > unsigned wake_count; > struct timer_list timer; > u32 reg_set; > @@ -582,12 +591,6 @@ struct intel_uncore { > u32 reg_post; > u32 val_reset; > } fw_domain[FW_DOMAIN_ID_COUNT]; > -#define FORCEWAKE_RENDER (1 << FW_DOMAIN_ID_RENDER) > -#define FORCEWAKE_BLITTER (1 << FW_DOMAIN_ID_BLITTER) > -#define FORCEWAKE_MEDIA (1 << FW_DOMAIN_ID_MEDIA) > -#define FORCEWAKE_ALL (FORCEWAKE_RENDER | \ > - FORCEWAKE_BLITTER | \ > - FORCEWAKE_MEDIA) > }; > > /* Iterate over initialised fw domains */ > @@ -2449,7 +2452,7 @@ extern void intel_uncore_init(struct drm_device *dev); > extern void intel_uncore_check_errors(struct drm_device *dev); > extern void intel_uncore_fini(struct drm_device *dev); > extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); > -const char *intel_uncore_forcewake_domain_to_str(const int domain_id); > +const char *intel_uncore_forcewake_domain_to_str(const enum fw_domain_id id); > void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, > unsigned fw_domains); > void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 509b9c9..e802486 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -49,7 +49,7 @@ static const char * const forcewake_domain_names[] = { > }; > > const char * > -intel_uncore_forcewake_domain_to_str(const int id) > +intel_uncore_forcewake_domain_to_str(const enum fw_domain_id id) > { > BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) != > FW_DOMAIN_ID_COUNT); > @@ -122,10 +122,10 @@ fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d) > } > > static void > -fw_domains_get(struct drm_i915_private *dev_priv, int fw_domains) > +fw_domains_get(struct drm_i915_private *dev_priv, enum fw_domains fw_domains) > { > struct intel_uncore_forcewake_domain *d; > - int id; > + enum fw_domain_id id; > > for_each_fw_domain_mask(d, fw_domains, dev_priv, id) { > fw_domain_wait_ack_clear(d); > @@ -136,10 +136,10 @@ fw_domains_get(struct drm_i915_private *dev_priv, int fw_domains) > } > > static void > -fw_domains_put(struct drm_i915_private *dev_priv, int fw_domains) > +fw_domains_put(struct drm_i915_private *dev_priv, enum fw_domains fw_domains) > { > struct intel_uncore_forcewake_domain *d; > - int id; > + enum fw_domain_id id; > > for_each_fw_domain_mask(d, fw_domains, dev_priv, id) > fw_domain_put(d); > @@ -149,7 +149,7 @@ static void > fw_domains_posting_read(struct drm_i915_private *dev_priv) > { > struct intel_uncore_forcewake_domain *d; > - int id; > + enum fw_domain_id id; > > /* No need to do for all, just do for first found */ > for_each_fw_domain(d, dev_priv, id) { > @@ -159,10 +159,10 @@ fw_domains_posting_read(struct drm_i915_private *dev_priv) > } > > static void > -fw_domains_reset(struct drm_i915_private *dev_priv, const unsigned fw_domains) > +fw_domains_reset(struct drm_i915_private *dev_priv, enum fw_domains fw_domains) > { > struct intel_uncore_forcewake_domain *d; > - int id; > + enum fw_domain_id id; > > for_each_fw_domain_mask(d, fw_domains, dev_priv, id) > fw_domain_reset(d); > @@ -181,7 +181,7 @@ static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) > } > > static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv, > - int fw_domains) > + enum fw_domains fw_domains) > { > fw_domains_get(dev_priv, fw_domains); > > @@ -199,7 +199,7 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) > } > > static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, > - int fw_domains) > + enum fw_domains fw_domains) > { > fw_domains_put(dev_priv, fw_domains); > gen6_gt_check_fifodbg(dev_priv); > @@ -251,9 +251,10 @@ static void intel_uncore_fw_release_timer(unsigned long arg) > void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - unsigned long irqflags, fw = 0; > + unsigned long irqflags; > struct intel_uncore_forcewake_domain *domain; > - int id; > + enum fw_domain_id id; > + enum fw_domains fw = 0; > > /* Hold uncore.lock across reset to prevent any register access > * with forcewake not set correctly > @@ -329,11 +330,11 @@ void intel_uncore_sanitize(struct drm_device *dev) > * intel_uncore_forcewake_put() at the end of the sequence. > */ > void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, > - unsigned fw_domains) > + enum fw_domains fw_domains) > { > unsigned long irqflags; > struct intel_uncore_forcewake_domain *domain; > - int id; > + enum fw_domain_id id; > > if (!dev_priv->uncore.funcs.force_wake_get) > return; > @@ -358,11 +359,11 @@ void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, > * see intel_uncore_forcewake_get() > */ > void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, > - unsigned fw_domains) > + enum fw_domains fw_domains) > { > unsigned long irqflags; > struct intel_uncore_forcewake_domain *domain; > - int id; > + enum fw_domain_id id; > > if (!dev_priv->uncore.funcs.force_wake_put) > return; > @@ -386,7 +387,7 @@ void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, > void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) > { > struct intel_uncore_forcewake_domain *domain; > - int id; > + enum fw_domain_id id; > > if (!dev_priv->uncore.funcs.force_wake_get) > return; > @@ -559,10 +560,10 @@ __gen2_read(64) > return val > > static inline void __force_wake_get(struct drm_i915_private *dev_priv, > - unsigned fw_domains) > + enum fw_domains fw_domains) > { > struct intel_uncore_forcewake_domain *domain; > - int id; > + enum fw_domain_id id; > > if (WARN_ON(!fw_domains)) > return; > @@ -626,7 +627,7 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ > #define __gen9_read(x) \ > static u##x \ > gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ > - unsigned fw_engine; \ > + enum fw_domains fw_engine; \ > GEN6_READ_HEADER(x); \ > if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) \ > fw_engine = 0; \ > @@ -826,7 +827,7 @@ static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg) > static void \ > gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \ > bool trace) { \ > - unsigned fw_engine; \ > + enum fw_domains fw_engine; \ > GEN6_WRITE_HEADER; \ > if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \ > is_gen9_shadowed(dev_priv, reg)) \ > @@ -892,7 +893,7 @@ do { \ > > > static void fw_domain_init(struct drm_i915_private *dev_priv, > - u32 domain_id, u32 reg_set, u32 reg_ack) > + enum fw_domain_id domain_id, u32 reg_set, u32 reg_ack) > { > struct intel_uncore_forcewake_domain *d; > > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 04/10] drm/i915: FIFO space query code refactor 2014-12-09 12:59 ` [PATCH 04/10] drm/i915: FIFO space query code refactor John.C.Harrison @ 2014-12-10 10:41 ` Daniel Vetter 2014-12-10 18:12 ` [PATCH v2] " Dave Gordon 0 siblings, 1 reply; 6+ messages in thread From: Daniel Vetter @ 2014-12-10 10:41 UTC (permalink / raw) To: John.C.Harrison; +Cc: Intel-GFX On Tue, Dec 09, 2014 at 12:59:07PM +0000, John.C.Harrison@Intel.com wrote: > From: Dave Gordon <david.s.gordon@intel.com> > > When querying the GTFIFOCTL register to check the FIFO space, the read value > must be masked. The operation is repeated explicitly in several places. This > change refactors the read-and-mask code into a function call. > > Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef > Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Looks like an unrelated patch and probably collides with Mika's forcewake refactoring. Please rebase on top of that series if still needed. -Daniel > --- > drivers/gpu/drm/i915/intel_uncore.c | 19 ++++++++++++------- > 1 file changed, 12 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 46de8d7..4021831 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -47,6 +47,13 @@ assert_device_not_suspended(struct drm_i915_private *dev_priv) > "Device suspended\n"); > } > > +static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) > +{ > + u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); > + > + return count & GT_FIFO_FREE_ENTRIES_MASK; > +} > + > static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) > { > /* w/a for a sporadic read returning 0 by waiting for the GT > @@ -154,16 +161,15 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) > /* On VLV, FIFO will be shared by both SW and HW. > * So, we need to read the FREE_ENTRIES everytime */ > if (IS_VALLEYVIEW(dev_priv->dev)) > - dev_priv->uncore.fifo_count = > - __raw_i915_read32(dev_priv, GTFIFOCTL) & > - GT_FIFO_FREE_ENTRIES_MASK; > + dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); > > if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { > int loop = 500; > - u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; > + u32 fifo = fifo_free_entries(dev_priv); > + > while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { > udelay(10); > - fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; > + fifo = fifo_free_entries(dev_priv); > } > if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) > ++ret; > @@ -505,8 +511,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) > > if (IS_GEN6(dev) || IS_GEN7(dev)) > dev_priv->uncore.fifo_count = > - __raw_i915_read32(dev_priv, GTFIFOCTL) & > - GT_FIFO_FREE_ENTRIES_MASK; > + fifo_free_entries(dev_priv); > } > > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2] drm/i915: FIFO space query code refactor 2014-12-10 10:41 ` [PATCH 04/10] drm/i915: FIFO space query code refactor Daniel Vetter @ 2014-12-10 18:12 ` Dave Gordon 2015-02-20 9:34 ` Mika Kuoppala 0 siblings, 1 reply; 6+ messages in thread From: Dave Gordon @ 2014-12-10 18:12 UTC (permalink / raw) To: intel-gfx When querying the GTFIFOCTL register to check the FIFO space, the read value must be masked. The operation is repeated explicitly in several places. This change refactors the read-and-mask code into a function call. v2: rebased on top of Mika's forcewake patch set, specifically: [PATCH 8/8] drm/i915: Enum forcewake domains and domain identifiers Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef Signed-off-by: Dave Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 66365e7..a0331a7 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -205,6 +205,13 @@ static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, gen6_gt_check_fifodbg(dev_priv); } +static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) +{ + u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); + + return count & GT_FIFO_FREE_ENTRIES_MASK; +} + static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) { int ret = 0; @@ -212,16 +219,15 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) /* On VLV, FIFO will be shared by both SW and HW. * So, we need to read the FREE_ENTRIES everytime */ if (IS_VALLEYVIEW(dev_priv->dev)) - dev_priv->uncore.fifo_count = - __raw_i915_read32(dev_priv, GTFIFOCTL) & - GT_FIFO_FREE_ENTRIES_MASK; + dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { int loop = 500; - u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; + u32 fifo = fifo_free_entries(dev_priv); + while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { udelay(10); - fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; + fifo = fifo_free_entries(dev_priv); } if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) ++ret; @@ -277,8 +283,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) if (IS_GEN6(dev) || IS_GEN7(dev)) dev_priv->uncore.fifo_count = - __raw_i915_read32(dev_priv, GTFIFOCTL) & - GT_FIFO_FREE_ENTRIES_MASK; + fifo_free_entries(dev_priv); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915: FIFO space query code refactor 2014-12-10 18:12 ` [PATCH v2] " Dave Gordon @ 2015-02-20 9:34 ` Mika Kuoppala 2015-02-23 15:46 ` Daniel Vetter 0 siblings, 1 reply; 6+ messages in thread From: Mika Kuoppala @ 2015-02-20 9:34 UTC (permalink / raw) To: Dave Gordon, intel-gfx Dave Gordon <david.s.gordon@intel.com> writes: > When querying the GTFIFOCTL register to check the FIFO space, the read value > must be masked. The operation is repeated explicitly in several places. This > change refactors the read-and-mask code into a function call. > > v2: rebased on top of Mika's forcewake patch set, specifically: > [PATCH 8/8] drm/i915: Enum forcewake domains and domain identifiers > > Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef > Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/intel_uncore.c | 19 ++++++++++++------- > 1 file changed, 12 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 66365e7..a0331a7 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -205,6 +205,13 @@ static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, > gen6_gt_check_fifodbg(dev_priv); > } > > +static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) > +{ > + u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); > + > + return count & GT_FIFO_FREE_ENTRIES_MASK; > +} > + > static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) > { > int ret = 0; > @@ -212,16 +219,15 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) > /* On VLV, FIFO will be shared by both SW and HW. > * So, we need to read the FREE_ENTRIES everytime */ > if (IS_VALLEYVIEW(dev_priv->dev)) > - dev_priv->uncore.fifo_count = > - __raw_i915_read32(dev_priv, GTFIFOCTL) & > - GT_FIFO_FREE_ENTRIES_MASK; > + dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); > > if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { > int loop = 500; > - u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; > + u32 fifo = fifo_free_entries(dev_priv); > + > while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { > udelay(10); > - fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; > + fifo = fifo_free_entries(dev_priv); > } > if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) > ++ret; > @@ -277,8 +283,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) > > if (IS_GEN6(dev) || IS_GEN7(dev)) > dev_priv->uncore.fifo_count = > - __raw_i915_read32(dev_priv, GTFIFOCTL) & > - GT_FIFO_FREE_ENTRIES_MASK; > + fifo_free_entries(dev_priv); > } > > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915: FIFO space query code refactor 2015-02-20 9:34 ` Mika Kuoppala @ 2015-02-23 15:46 ` Daniel Vetter 0 siblings, 0 replies; 6+ messages in thread From: Daniel Vetter @ 2015-02-23 15:46 UTC (permalink / raw) To: Mika Kuoppala; +Cc: intel-gfx On Fri, Feb 20, 2015 at 11:34:29AM +0200, Mika Kuoppala wrote: > Dave Gordon <david.s.gordon@intel.com> writes: > > > When querying the GTFIFOCTL register to check the FIFO space, the read value > > must be masked. The operation is repeated explicitly in several places. This > > change refactors the read-and-mask code into a function call. > > > > v2: rebased on top of Mika's forcewake patch set, specifically: > > [PATCH 8/8] drm/i915: Enum forcewake domains and domain identifiers > > > > Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef > > Signed-off-by: Dave Gordon <david.s.gordon@intel.com> > > Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-02-23 15:45 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-12-18 16:45 [PATCH v2] drm/i915: FIFO space query code refactor Dave Gordon 2014-12-19 10:11 ` shuang.he -- strict thread matches above, loose matches on Subject: below -- 2014-12-18 16:48 [PATCH v2*] " Dave Gordon 2014-12-09 12:59 [PATCH 00/10] Prep work patches for GPU scheduler John.C.Harrison 2014-12-09 12:59 ` [PATCH 04/10] drm/i915: FIFO space query code refactor John.C.Harrison 2014-12-09 13:32 ` [PATCH 8/8] drm/i915: Enum forcewake domains and domain identifiers Jani Nikula 2014-12-10 10:41 ` [PATCH 04/10] drm/i915: FIFO space query code refactor Daniel Vetter 2014-12-10 18:12 ` [PATCH v2] " Dave Gordon 2015-02-20 9:34 ` Mika Kuoppala 2015-02-23 15:46 ` Daniel Vetter
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