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* [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a
@ 2015-01-09  3:59 Ben Widawsky
  2015-01-09  3:59 ` [PATCH 2/4] drm/i915/skl: Implement WaHdcCtxNonCoherent Ben Widawsky
                   ` (3 more replies)
  0 siblings, 4 replies; 8+ messages in thread
From: Ben Widawsky @ 2015-01-09  3:59 UTC (permalink / raw)
  To: Intel GFX; +Cc: Ben Widawsky, Ben Widawsky

Implements a required workaround whose implications aren't entirely clear to me
from the description. In particular I do not know if this effects legacy
contexts, execlists, or both.

I couldn't find a real workaround name, so I made up:
WaHdcCtxNonCoherent

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_reg.h         | 5 +++--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0f32fd1a..dabac96 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5219,9 +5219,10 @@ enum punit_power_well {
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0				0x7300
-#define  HDC_FORCE_NON_COHERENT			(1<<4)
-#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
+#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
+#define  HDC_FORCE_CTX_NON_COHERENT		(1<<5)
+#define  HDC_FORCE_NON_COHERENT			(1<<4)
 
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 12a36f0..62318a4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -790,8 +790,10 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
 	 */
 	/* WaForceEnableNonCoherent:bdw */
 	/* WaHdcDisableFetchWhenMasked:bdw */
+	/* WaHdcCtxNonCoherent:bdw */
 	/* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
 	WA_SET_BIT_MASKED(HDC_CHICKEN0,
+			  HDC_FORCE_CTX_NON_COHERENT |
 			  HDC_FORCE_NON_COHERENT |
 			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 			  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
-- 
2.2.1

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^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH 2/4] drm/i915/skl: Implement WaHdcCtxNonCoherent
  2015-01-09  3:59 [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a Ben Widawsky
@ 2015-01-09  3:59 ` Ben Widawsky
  2015-01-09  3:59 ` [PATCH 3/4] drm/i915/skl: Implement WaDisablePartialInstShootdown Ben Widawsky
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 8+ messages in thread
From: Ben Widawsky @ 2015-01-09  3:59 UTC (permalink / raw)
  To: Intel GFX; +Cc: Ben Widawsky, Ben Widawsky

Cc: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 62318a4..b8a445b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -841,6 +841,17 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
 	return 0;
 }
 
+static int skl_init_workarounds(struct intel_engine_cs *ring)
+{
+	struct drm_device *dev = ring->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* WaHdcCtxNonCoherent:skl */
+	WA_SET_BIT_MASKED(HDC_CHICKEN0, HDC_FORCE_CTX_NON_COHERENT);
+
+	return 0;
+}
+
 int init_workarounds_ring(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
@@ -856,6 +867,9 @@ int init_workarounds_ring(struct intel_engine_cs *ring)
 	if (IS_CHERRYVIEW(dev))
 		return chv_init_workarounds(ring);
 
+	if (IS_SKYLAKE(dev))
+		return skl_init_workarounds(ring);
+
 	return 0;
 }
 
-- 
2.2.1

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^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH 3/4] drm/i915/skl: Implement WaDisablePartialInstShootdown
  2015-01-09  3:59 [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a Ben Widawsky
  2015-01-09  3:59 ` [PATCH 2/4] drm/i915/skl: Implement WaHdcCtxNonCoherent Ben Widawsky
@ 2015-01-09  3:59 ` Ben Widawsky
  2015-01-09  3:59 ` [PATCH 4/4] drm/i915: Add a fallback for unimplemented gen9 w/a Ben Widawsky
  2015-02-02 12:33 ` [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a Ville Syrjälä
  3 siblings, 0 replies; 8+ messages in thread
From: Ben Widawsky @ 2015-01-09  3:59 UTC (permalink / raw)
  To: Intel GFX; +Cc: Ben Widawsky, Ben Widawsky

Cc: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b8a445b..e14748d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -846,6 +846,10 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
+	/* WaDisablePartialInstShootdown:skl */
+	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
+			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
+
 	/* WaHdcCtxNonCoherent:skl */
 	WA_SET_BIT_MASKED(HDC_CHICKEN0, HDC_FORCE_CTX_NON_COHERENT);
 
-- 
2.2.1

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^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH 4/4] drm/i915: Add a fallback for unimplemented gen9 w/a
  2015-01-09  3:59 [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a Ben Widawsky
  2015-01-09  3:59 ` [PATCH 2/4] drm/i915/skl: Implement WaHdcCtxNonCoherent Ben Widawsky
  2015-01-09  3:59 ` [PATCH 3/4] drm/i915/skl: Implement WaDisablePartialInstShootdown Ben Widawsky
@ 2015-01-09  3:59 ` Ben Widawsky
  2015-01-09  9:35   ` shuang.he
  2015-02-02 12:33 ` [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a Ville Syrjälä
  3 siblings, 1 reply; 8+ messages in thread
From: Ben Widawsky @ 2015-01-09  3:59 UTC (permalink / raw)
  To: Intel GFX; +Cc: Ben Widawsky, Ben Widawsky

We know certain future platforms need things. Don't let them go unnoticed as
they did for SKL by adding an error message and falling back to the possibly
more conservative SKL values.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e14748d..557204b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -873,6 +873,10 @@ int init_workarounds_ring(struct intel_engine_cs *ring)
 
 	if (IS_SKYLAKE(dev))
 		return skl_init_workarounds(ring);
+	else if (INTEL_INFO(dev)->gen == 9) {
+		DRM_ERROR("Possibly missing workarounds\n");
+		return skl_init_workarounds(ring);
+	}
 
 	return 0;
 }
-- 
2.2.1

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^ permalink raw reply related	[flat|nested] 8+ messages in thread
* Re: [PATCH 4/4] drm/i915: Add a fallback for unimplemented gen9 w/a
  2015-01-09  3:59 ` [PATCH 4/4] drm/i915: Add a fallback for unimplemented gen9 w/a Ben Widawsky
@ 2015-01-09  9:35   ` shuang.he
  0 siblings, 0 replies; 8+ messages in thread
From: shuang.he @ 2015-01-09  9:35 UTC (permalink / raw)
  To: shuang.he, intel-gfx, benjamin.widawsky

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -31              363/364              332/364
ILK                 -20              364/366              344/366
SNB              +4-64              443/450              383/450
IVB                 -46              496/498              450/498
BYT                 -8              288/289              280/289
HSW              +19-65              542/564              496/564
BDW                 -33              415/417              382/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(5, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_pread_after_blit_interruptible      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M25)
 PNV  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M25)
 PNV  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M25)
 PNV  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M25)
 PNV  igt_gem_pread_after_blit_normal      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M25)
 PNV  igt_gem_pread_after_blit_normal-display      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M25)
 PNV  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M25)
 PNV  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M25)
 ILK  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(5, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(5, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(5, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(5, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(5, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(5, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(5, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(5, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(5, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(5, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(5, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(5, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_pread_after_blit_interruptible      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_normal      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_normal-display      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 SNB  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-early-read-forked      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-forked      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-forked      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-early-read-forked      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-early-read-forked      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-forked      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(5, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_pread_after_blit_interruptible      NRUN(2, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_normal      NRUN(2, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_normal-display      NRUN(2, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_kms_cursor_crc_cursor-size-change      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_kms_flip_dpms-vs-vblank-race      DMESG_WARN(3, M35M22)PASS(5, M35M22)      PASS(1, M35)
 SNB  igt_kms_flip_dpms-vs-vblank-race-interruptible      DMESG_WARN(2, M35M22)PASS(6, M35M22)      PASS(1, M35)
*SNB  igt_kms_flip_event_leak      NSPT(4, M35M22)PASS(1, M35)      FAIL(1, M35)
 SNB  igt_kms_flip_modeset-vs-vblank-race      DMESG_WARN(4, M35M22)PASS(5, M35M22)      PASS(1, M35)
 SNB  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_kms_plane_plane-position-hole-pipe-B-plane-1      DMESG_WARN(1, M35)PASS(9, M35M22)      PASS(1, M35)
 SNB  igt_kms_rotation_crc_primary-rotation      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_kms_rotation_crc_sprite-rotation      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_cursor      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_cursor-dpms      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_dpms-non-lpsp      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_drm-resources-equal      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_fences      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_fences-dpms      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_gem-execbuf      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_gem-mmap-cpu      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_gem-mmap-gtt      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_gem-pread      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_i2c      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_modeset-non-lpsp      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_pci-d3-state      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_rte      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 IVB  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-bcs-early-read-forked      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-forked      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-forked      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-rcs-early-read-forked      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-early-read-forked      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-forked      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-early-read-forked      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-forked      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(5, M21M34M4)PASS(1, M34)      NSPT(1, M4)
 IVB  igt_gem_pread_after_blit_interruptible      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M4)
 IVB  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M4)
 IVB  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M4)
 IVB  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M4)
 IVB  igt_gem_pread_after_blit_normal      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M4)
 IVB  igt_gem_pread_after_blit_normal-display      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M4)
 IVB  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M4)
 IVB  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M4)
*IVB  igt_kms_plane_plane-position-hole-pipe-B-plane-2      PASS(2, M34M4)      DMESG_WARN(1, M4)
*IVB  igt_kms_rotation_crc_primary-rotation      PASS(2, M34M4)      TIMEOUT(1, M4)
 BYT  igt_gem_pread_after_blit_interruptible      NRUN(2, M51)PASS(1, M48)      NRUN(1, M51)
 BYT  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M51)PASS(1, M48)      NRUN(1, M51)
 BYT  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M51)PASS(1, M48)      NRUN(1, M51)
 BYT  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M51)PASS(1, M48)      NRUN(1, M51)
 BYT  igt_gem_pread_after_blit_normal      NRUN(2, M51)PASS(1, M48)      NRUN(1, M51)
 BYT  igt_gem_pread_after_blit_normal-display      NRUN(2, M51)PASS(1, M48)      NRUN(1, M51)
 BYT  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M51)PASS(1, M48)      NRUN(1, M51)
 BYT  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M51)PASS(1, M48)      NRUN(1, M51)
 HSW  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-bcs-early-read-forked      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-forked      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-forked      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-rcs-early-read-forked      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-early-read-forked      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-forked      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-early-read-forked      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-forked      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(5, M19M20)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_gem_pread_after_blit_interruptible      NRUN(2, M19)PASS(1, M40)      NRUN(1, M19)
 HSW  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M19)PASS(1, M40)      NRUN(1, M19)
 HSW  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M19)PASS(1, M40)      NRUN(1, M19)
 HSW  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M19)PASS(1, M40)      NRUN(1, M19)
 HSW  igt_gem_pread_after_blit_normal      NRUN(2, M19)PASS(1, M40)      NRUN(1, M19)
 HSW  igt_gem_pread_after_blit_normal-display      NRUN(2, M19)PASS(1, M40)      NRUN(1, M19)
 HSW  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M19)PASS(1, M40)      NRUN(1, M19)
 HSW  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M19)PASS(1, M40)      NRUN(1, M19)
 HSW  igt_kms_cursor_crc_cursor-size-change      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_kms_fence_pin_leak      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_kms_flip_dpms-vs-vblank-race      DMESG_WARN(1, M40)PASS(5, M19M20)      PASS(1, M19)
 HSW  igt_kms_flip_dpms-vs-vblank-race-interruptible      DMESG_WARN(2, M40)PASS(5, M19M20)      PASS(1, M19)
 HSW  igt_kms_flip_event_leak      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_kms_flip_flip-vs-dpms-off-vs-modeset      DMESG_WARN(1, M40)PASS(5, M19M20)      PASS(1, M19)
 HSW  igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible      DMESG_WARN(2, M40M19)PASS(5, M19M20)      PASS(1, M19)
 HSW  igt_kms_flip_modeset-vs-vblank-race      DMESG_WARN(1, M40)PASS(5, M19M20)      PASS(1, M19)
 HSW  igt_kms_flip_modeset-vs-vblank-race-interruptible      DMESG_WARN(1, M40)PASS(5, M19M20)      PASS(1, M19)
 HSW  igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset-interruptible      DMESG_WARN(2, M40)PASS(6, M19M20)      PASS(1, M19)
 HSW  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_kms_pipe_crc_basic_read-crc-pipe-B      TIMEOUT(1, M40)PASS(3, M19)      PASS(1, M19)
 HSW  igt_kms_pipe_crc_basic_read-crc-pipe-B-frame-sequence      TIMEOUT(1, M40)PASS(3, M19)      PASS(1, M19)
 HSW  igt_kms_pipe_crc_basic_read-crc-pipe-C      TIMEOUT(1, M40)PASS(3, M19)      PASS(1, M19)
 HSW  igt_kms_pipe_crc_basic_read-crc-pipe-C-frame-sequence      TIMEOUT(1, M40)PASS(3, M19)      PASS(1, M19)
 HSW  igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-1      TIMEOUT(1, M40)PASS(3, M19)      PASS(1, M19)
 HSW  igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-2      TIMEOUT(1, M40)PASS(3, M19)      PASS(1, M19)
 HSW  igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-1      TIMEOUT(1, M40)PASS(4, M19M20)      PASS(1, M19)
 HSW  igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-2      TIMEOUT(1, M40)PASS(4, M19M20)      PASS(1, M19)
 HSW  igt_kms_plane_plane-panning-bottom-right-pipe-C-plane-1      TIMEOUT(3, M40)PASS(7, M19M40M20)      PASS(1, M19)
 HSW  igt_kms_setmode_invalid-clone-exclusive-crtc      DMESG_WARN(1, M40)PASS(3, M19)      PASS(1, M19)
 HSW  igt_pm_lpsp_non-edp      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_cursor      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_cursor-dpms      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_dpms-non-lpsp      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_drm-resources-equal      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_fences      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_fences-dpms      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_gem-execbuf      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_gem-mmap-cpu      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_gem-mmap-gtt      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_gem-pread      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_i2c      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_modeset-non-lpsp      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(4, M19)DMESG_WARN(1, M40)PASS(5, M40M20)      NSPT(1, M19)
 HSW  igt_pm_rpm_pci-d3-state      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_pm_rpm_rte      NSPT(3, M19)PASS(1, M40)      NSPT(1, M19)
 HSW  igt_kms_flip_flip-vs-rmfb      DMESG_WARN(1, M40)PASS(4, M19)      PASS(1, M19)
 HSW  igt_kms_flip_flip-vs-rmfb-interruptible      DMESG_WARN(1, M40)PASS(3, M19)      PASS(1, M19)
 BDW  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(5, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_pread_after_blit_interruptible      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_normal      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_normal-display      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
*BDW  igt_gem_multi_bsd_sync_loop      PASS(6, M30M28)      DMESG_WARN(1, M30)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a
  2015-01-09  3:59 [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a Ben Widawsky
                   ` (2 preceding siblings ...)
  2015-01-09  3:59 ` [PATCH 4/4] drm/i915: Add a fallback for unimplemented gen9 w/a Ben Widawsky
@ 2015-02-02 12:33 ` Ville Syrjälä
  2015-02-02 13:21   ` Damien Lespiau
  3 siblings, 1 reply; 8+ messages in thread
From: Ville Syrjälä @ 2015-02-02 12:33 UTC (permalink / raw)
  To: Ben Widawsky; +Cc: Intel GFX, Ben Widawsky

On Thu, Jan 08, 2015 at 07:59:10PM -0800, Ben Widawsky wrote:
> Implements a required workaround whose implications aren't entirely clear to me
> from the description. In particular I do not know if this effects legacy
> contexts, execlists, or both.
> 
> I couldn't find a real workaround name, so I made up:
> WaHdcCtxNonCoherent

I don't think we want to make up w/a names. Might cause someone to
conclude that the w/a is no longer needed if they can't find the
name in the w/a database or bspec. So maybe just add a small quote from
bspec, or leave it without explanation forcing people to check bspec
if they want to find out why it's there.

I suppose one option would be to add a private namespace for our made
up w/a names. But I don't really see a point in making up w/a names
if we don't have a some documentation telling people what those names
actually mean.

So with the made up w/a name removed:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 5 +++--
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0f32fd1a..dabac96 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5219,9 +5219,10 @@ enum punit_power_well {
>  
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0				0x7300
> -#define  HDC_FORCE_NON_COHERENT			(1<<4)
> -#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
>  #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
> +#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
> +#define  HDC_FORCE_CTX_NON_COHERENT		(1<<5)
> +#define  HDC_FORCE_NON_COHERENT			(1<<4)
>  
>  /* WaCatErrorRejectionIssue */
>  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 12a36f0..62318a4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -790,8 +790,10 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>  	 */
>  	/* WaForceEnableNonCoherent:bdw */
>  	/* WaHdcDisableFetchWhenMasked:bdw */
> +	/* WaHdcCtxNonCoherent:bdw */
>  	/* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0,
> +			  HDC_FORCE_CTX_NON_COHERENT |
>  			  HDC_FORCE_NON_COHERENT |
>  			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
>  			  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
> -- 
> 2.2.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a
  2015-02-02 12:33 ` [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a Ville Syrjälä
@ 2015-02-02 13:21   ` Damien Lespiau
  2015-02-05  4:09     ` Ben Widawsky
  0 siblings, 1 reply; 8+ messages in thread
From: Damien Lespiau @ 2015-02-02 13:21 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: Intel GFX, Ben Widawsky, Ben Widawsky

On Mon, Feb 02, 2015 at 02:33:48PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 08, 2015 at 07:59:10PM -0800, Ben Widawsky wrote:
> > Implements a required workaround whose implications aren't entirely clear to me
> > from the description. In particular I do not know if this effects legacy
> > contexts, execlists, or both.
> > 
> > I couldn't find a real workaround name, so I made up:
> > WaHdcCtxNonCoherent
> 
> I don't think we want to make up w/a names. Might cause someone to
> conclude that the w/a is no longer needed if they can't find the
> name in the w/a database or bspec. So maybe just add a small quote from
> bspec, or leave it without explanation forcing people to check bspec
> if they want to find out why it's there.
> 
> I suppose one option would be to add a private namespace for our made
> up w/a names. But I don't really see a point in making up w/a names
> if we don't have a some documentation telling people what those names
> actually mean.
> 
> So with the made up w/a name removed:
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

If you want to believe my version, it's called WaForceContextSaveRestoreNonCoherent

http://lists.freedesktop.org/archives/intel-gfx/2015-January/059086.html

-- 
Damien
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a
  2015-02-02 13:21   ` Damien Lespiau
@ 2015-02-05  4:09     ` Ben Widawsky
  0 siblings, 0 replies; 8+ messages in thread
From: Ben Widawsky @ 2015-02-05  4:09 UTC (permalink / raw)
  To: Damien Lespiau; +Cc: Intel GFX, Ben Widawsky

On Mon, Feb 02, 2015 at 01:21:19PM +0000, Damien Lespiau wrote:
> On Mon, Feb 02, 2015 at 02:33:48PM +0200, Ville Syrjälä wrote:
> > On Thu, Jan 08, 2015 at 07:59:10PM -0800, Ben Widawsky wrote:
> > > Implements a required workaround whose implications aren't entirely clear to me
> > > from the description. In particular I do not know if this effects legacy
> > > contexts, execlists, or both.
> > > 
> > > I couldn't find a real workaround name, so I made up:
> > > WaHdcCtxNonCoherent
> > 
> > I don't think we want to make up w/a names. Might cause someone to
> > conclude that the w/a is no longer needed if they can't find the
> > name in the w/a database or bspec. So maybe just add a small quote from
> > bspec, or leave it without explanation forcing people to check bspec
> > if they want to find out why it's there.
> > 
> > I suppose one option would be to add a private namespace for our made
> > up w/a names. But I don't really see a point in making up w/a names
> > if we don't have a some documentation telling people what those names
> > actually mean.
> > 
> > So with the made up w/a name removed:
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> If you want to believe my version, it's called WaForceContextSaveRestoreNonCoherent
> 
> http://lists.freedesktop.org/archives/intel-gfx/2015-January/059086.html
> 

If you reorder the defines as I did, it's
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

It really irks me that the defines are out of place. Or you can send the v2 of
my patch :D
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^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2015-02-05  4:09 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-01-09  3:59 [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a Ben Widawsky
2015-01-09  3:59 ` [PATCH 2/4] drm/i915/skl: Implement WaHdcCtxNonCoherent Ben Widawsky
2015-01-09  3:59 ` [PATCH 3/4] drm/i915/skl: Implement WaDisablePartialInstShootdown Ben Widawsky
2015-01-09  3:59 ` [PATCH 4/4] drm/i915: Add a fallback for unimplemented gen9 w/a Ben Widawsky
2015-01-09  9:35   ` shuang.he
2015-02-02 12:33 ` [PATCH 1/4] drm/i915/bdw: Implement non-coherent ctx w/a Ville Syrjälä
2015-02-02 13:21   ` Damien Lespiau
2015-02-05  4:09     ` Ben Widawsky

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