From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, chris@chris-wilson.co.uk
Subject: Re: [PATCH] drm/i915: Insert a command barrier on BLT/BSD cache flushes
Date: 22 Jan 2015 14:41:06 -0800 [thread overview]
Message-ID: <898e4a$d7bjkn@FMSMGA003.fm.intel.com> (raw)
In-Reply-To: <1421932438-22575-1-git-send-email-chris@chris-wilson.co.uk>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5625
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -2 353/353 351/353
ILK 200/200 200/200
SNB 400/422 400/422
IVB 487/487 487/487
BYT 296/296 296/296
HSW 508/508 508/508
BDW 401/402 401/402
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt_gen3_render_linear_blits PASS(4, M25M23) NRUN(1, M23)
*PNV igt_gen3_render_mixed_blits PASS(3, M25M23) CRASH(1, M23)
Note: You need to pay more attention to line start with '*'
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prev parent reply other threads:[~2015-01-22 22:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-22 13:13 [PATCH] drm/i915: Insert a command barrier on BLT/BSD cache flushes Chris Wilson
2015-01-22 13:24 ` [Intel-gfx] " Daniel Vetter
2015-01-22 13:32 ` Chris Wilson
2015-01-22 13:42 ` [PATCH v2] " Chris Wilson
2015-01-22 22:45 ` shuang.he
2015-02-09 16:00 ` [Intel-gfx] " Jani Nikula
2015-02-09 16:07 ` Chris Wilson
2015-02-09 18:15 ` Jani Nikula
2015-01-22 22:41 ` shuang.he [this message]
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