[PATCH] drm/i915: Shift driver's HWSP usage out of reserved range

[PATCH] drm/i915: Shift driver's HWSP usage out of reserved range

[Thomas Daniel]

As of Gen6, the general purpose area of the hardware status page has shrunk and
now begins at dword 0x30.  i915 driver uses dword 0x20 to store the seqno which
is now reserved.  So shift our HWSP dwords up into the general purpose range
before this bites us.

Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.h |    7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index b6c484f..39183fc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -373,11 +373,12 @@ intel_write_status_page(struct intel_engine_cs *ring,
  * 0x06: ring 2 head pointer (915-class)
  * 0x10-0x1b: Context status DWords (GM45)
  * 0x1f: Last written status offset. (GM45)
+ * 0x20-0x2f: Reserved (Gen6+)
  *
- * The area from dword 0x20 to 0x3ff is available for driver usage.
+ * The area from dword 0x30 to 0x3ff is available for driver usage.
  */
-#define I915_GEM_HWS_INDEX		0x20
-#define I915_GEM_HWS_SCRATCH_INDEX	0x30
+#define I915_GEM_HWS_INDEX		0x30
+#define I915_GEM_HWS_SCRATCH_INDEX	0x40
 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 
 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
-- 
1.7.9.5

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Re: [PATCH] drm/i915: Shift driver's HWSP usage out of reserved range

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5787
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -1              277/277              276/277
ILK                                  313/313              313/313
SNB                                  309/309              309/309
IVB                                  382/382              382/382
BYT                                  296/296              296/296
HSW                                  425/425              425/425
BDW                 -1              318/318              317/318
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt_gem_userptr_blits_coherency-unsync      CRASH(2)PASS(2)      CRASH(1)PASS(1)
*BDW  igt_gem_gtt_hog      PASS(6)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH] drm/i915: Shift driver's HWSP usage out of reserved range

[Dave Gordon]

On 18/02/15 11:48, Thomas Daniel wrote:
> As of Gen6, the general purpose area of the hardware status page has shrunk and
> now begins at dword 0x30.  i915 driver uses dword 0x20 to store the seqno which
> is now reserved.  So shift our HWSP dwords up into the general purpose range
> before this bites us.
> 
> Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.h |    7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index b6c484f..39183fc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -373,11 +373,12 @@ intel_write_status_page(struct intel_engine_cs *ring,
>   * 0x06: ring 2 head pointer (915-class)
>   * 0x10-0x1b: Context status DWords (GM45)
>   * 0x1f: Last written status offset. (GM45)
> + * 0x20-0x2f: Reserved (Gen6+)
>   *
> - * The area from dword 0x20 to 0x3ff is available for driver usage.
> + * The area from dword 0x30 to 0x3ff is available for driver usage.
>   */
> -#define I915_GEM_HWS_INDEX		0x20
> -#define I915_GEM_HWS_SCRATCH_INDEX	0x30
> +#define I915_GEM_HWS_INDEX		0x30
> +#define I915_GEM_HWS_SCRATCH_INDEX	0x40
>  #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
>  
>  void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);

Well, nothing much can go wnorg here!

Reviewed-by: Dave Gordon <david.s.gordon@intel.com>

But just FYI, these will all get changed again when we add support for
preemption (: because then we'll need more than one place to store
'sequence numbers' :)

.Dave.

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Re: [PATCH] drm/i915: Shift driver's HWSP usage out of reserved range

[Daniel Vetter]

On Thu, Feb 19, 2015 at 02:58:48PM +0000, Dave Gordon wrote:
> On 18/02/15 11:48, Thomas Daniel wrote:
> > As of Gen6, the general purpose area of the hardware status page has shrunk and
> > now begins at dword 0x30.  i915 driver uses dword 0x20 to store the seqno which
> > is now reserved.  So shift our HWSP dwords up into the general purpose range
> > before this bites us.

It would be really interesting to know what exactly the hw does with
offsets below 0x30 ... it might explain some of the bugs we've seen. Can
you please digg that out so that I can amend the commit message?

> > Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.h |    7 ++++---
> >  1 file changed, 4 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > index b6c484f..39183fc 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > @@ -373,11 +373,12 @@ intel_write_status_page(struct intel_engine_cs *ring,
> >   * 0x06: ring 2 head pointer (915-class)
> >   * 0x10-0x1b: Context status DWords (GM45)
> >   * 0x1f: Last written status offset. (GM45)
> > + * 0x20-0x2f: Reserved (Gen6+)
> >   *
> > - * The area from dword 0x20 to 0x3ff is available for driver usage.
> > + * The area from dword 0x30 to 0x3ff is available for driver usage.
> >   */
> > -#define I915_GEM_HWS_INDEX		0x20
> > -#define I915_GEM_HWS_SCRATCH_INDEX	0x30
> > +#define I915_GEM_HWS_INDEX		0x30
> > +#define I915_GEM_HWS_SCRATCH_INDEX	0x40
> >  #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
> >  
> >  void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
> 
> Well, nothing much can go wnorg here!
> 
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>

Anyway for now queued for -next, thanks for the patch.
-Daniel

> 
> But just FYI, these will all get changed again when we add support for
> preemption (: because then we'll need more than one place to store
> 'sequence numbers' :)
> 
> .Dave.
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH] drm/i915: Shift driver's HWSP usage out of reserved range

[Daniel, Thomas]

> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: Monday, February 23, 2015 11:28 PM
> To: Gordon, David S
> Cc: Daniel, Thomas; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Shift driver's HWSP usage out of
> reserved range
> 
> On Thu, Feb 19, 2015 at 02:58:48PM +0000, Dave Gordon wrote:
> > On 18/02/15 11:48, Thomas Daniel wrote:
> > > As of Gen6, the general purpose area of the hardware status page has shrunk
> and
> > > now begins at dword 0x30.  i915 driver uses dword 0x20 to store the seqno
> which
> > > is now reserved.  So shift our HWSP dwords up into the general purpose
> range
> > > before this bites us.
> 
> It would be really interesting to know what exactly the hw does with
> offsets below 0x30 ... it might explain some of the bugs we've seen. Can
> you please digg that out so that I can amend the commit message?

All documentation I've seen just says "Reserved" for current hardware including SKL so we can't rely on any particular usage.  That's why I just put "Reserved" for these dwords in the comment.

Thomas.


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Re: [PATCH] drm/i915: Shift driver's HWSP usage out of reserved range

[Daniel Vetter]

On Tue, Feb 24, 2015 at 10:20:17AM +0000, Daniel, Thomas wrote:
> > -----Original Message-----
> > From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
> > Sent: Monday, February 23, 2015 11:28 PM
> > To: Gordon, David S
> > Cc: Daniel, Thomas; intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Shift driver's HWSP usage out of
> > reserved range
> > 
> > On Thu, Feb 19, 2015 at 02:58:48PM +0000, Dave Gordon wrote:
> > > On 18/02/15 11:48, Thomas Daniel wrote:
> > > > As of Gen6, the general purpose area of the hardware status page has shrunk
> > and
> > > > now begins at dword 0x30.  i915 driver uses dword 0x20 to store the seqno
> > which
> > > > is now reserved.  So shift our HWSP dwords up into the general purpose
> > range
> > > > before this bites us.
> > 
> > It would be really interesting to know what exactly the hw does with
> > offsets below 0x30 ... it might explain some of the bugs we've seen. Can
> > you please digg that out so that I can amend the commit message?
> 
> All documentation I've seen just says "Reserved" for current hardware
> including SKL so we can't rely on any particular usage.  That's why I
> just put "Reserved" for these dwords in the comment.

Thanks for the clarification, I've ammended the commit message.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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