From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: Enable aspect/centering panel fitting for Ironlake. Date: Thu, 05 Aug 2010 09:05:15 +0100 Message-ID: <89k83a$965hlv@azsmga001.ch.intel.com> References: <1280930641-24502-1-git-send-email-chris@chris-wilson.co.uk> <20100805011126.GA780@zhen-devel.sh.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id CFAA89E93B for ; Thu, 5 Aug 2010 01:05:22 -0700 (PDT) In-Reply-To: <20100805011126.GA780@zhen-devel.sh.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Zhenyu Wang Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, 5 Aug 2010 09:11:26 +0800, Zhenyu Wang wrote: > On 2010.08.04 15:04:01 +0100, Chris Wilson wrote: > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 07f893f..9b5fab4 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -1914,15 +1914,13 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) > > /* Enable panel fitting for LVDS */ > > if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) > > || HAS_eDP || intel_pch_has_edp(crtc)) { > > - temp = I915_READ(pf_ctl_reg); > > - I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3); > > - > > - /* currently full aspect */ > > - I915_WRITE(pf_win_pos, 0); > > - > > - I915_WRITE(pf_win_size, > > - (dev_priv->panel_fixed_mode->hdisplay << 16) | > > - (dev_priv->panel_fixed_mode->vdisplay)); > > + if (dev_priv->pch_pf_size) { > > + temp = I915_READ(pf_ctl_reg); > > + I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3); > > + I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos); > > + I915_WRITE(pf_win_size, dev_priv->pch_pf_size); > > + } else > > + I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE); > > } > > So this breaks panel fitting setting on eDP... Please illuminate the poor ignorant fool (that's me) what the requirements for eDP are. Even better in patch form. ;-) Does eDP require panel fitting always? -- Chris Wilson, Intel Open Source Technology Centre