Re: [Intel-gfx] [PATCH 3/6] drm/i915/display/adl_p: Implement Wa_16011168373

Gwan-gyeong Mun
2021-06-23T19:21:22Z

Looks good to me.

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

On 6/16/21 11:31 PM, José Roberto de Souza wrote:
> Another WA that is required for PSR2.
>
> BSpec: 54369
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index c8d56387d9233..e508816911fad 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1112,6 +1112,14 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
> intel_dp->psr.psr2_sel_fetch_enabled ?
> IGNORE_PSR2_HW_TRACKING : 0);
> +
> + /* Wa_16011168373:adlp */
> + if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
> + intel_dp->psr.psr2_enabled)
> + intel_de_rmw(dev_priv,
> + TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
> + TRANS_SET_CONTEXT_LATENCY_MASK,
> + TRANS_SET_CONTEXT_LATENCY_VALUE(1));
> }
>
> static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> @@ -1289,6 +1297,13 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>
> + /* Wa_16011168373:adlp */
> + if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
> + intel_dp->psr.psr2_enabled)
> + intel_de_rmw(dev_priv,
> + TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
> + TRANS_SET_CONTEXT_LATENCY_MASK, 0);
> +
> /* Disable PSR on Sink */
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4a98e49c58812..568e5f108e2c4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10368,6 +10368,14 @@ enum skl_power_gate {
> #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
> /* See DP_MSA_MISC_* for the bit definitions */
>
> +#define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
> +#define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
> +#define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
> +#define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
> +#define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY)
> +#define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
> +#define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
> +
> /* LCPLL Control */
> #define LCPLL_CTL _MMIO(0x130040)
> #define LCPLL_PLL_DISABLE (1 << 31)