From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68904C433EF for ; Tue, 21 Sep 2021 14:36:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3773961183 for ; Tue, 21 Sep 2021 14:36:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3773961183 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C8736E9B7; Tue, 21 Sep 2021 14:36:12 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id E7F786E9B5; Tue, 21 Sep 2021 14:36:10 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10113"; a="203527677" X-IronPort-AV: E=Sophos;i="5.85,311,1624345200"; d="scan'208";a="203527677" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2021 07:35:30 -0700 X-IronPort-AV: E=Sophos;i="5.85,311,1624345200"; d="scan'208";a="556963770" Received: from ekyne-mobl.ger.corp.intel.com (HELO [10.213.200.64]) ([10.213.200.64]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2021 07:35:29 -0700 To: Matt Roper , intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Chris Wilson References: <20210910201030.3436066-1-matthew.d.roper@intel.com> <20210910201030.3436066-5-matthew.d.roper@intel.com> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc Message-ID: <939bbb3c-9814-a6e7-19b3-7c0d6b068ade@linux.intel.com> Date: Tue, 21 Sep 2021 15:35:27 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210910201030.3436066-5-matthew.d.roper@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Intel-gfx] [PATCH v2 4/6] drm/i915/uncore: Drop gen11/gen12 mmio write handlers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 10/09/2021 21:10, Matt Roper wrote: > Now that the reference to the shadow table is stored within the uncore, > we don't need to generate separate fwtable, gen11_fwtable, and > gen12_fwtable variants of the register write functions; a single > 'fwtable' implementation will work for all of those platforms now. > > While consolidating the functions, gen11/gen12 pick up a > NEEDS_FORCE_WAKE() check that they didn't have before, allowing them to > bypass a lot of forcewake/shadow checking for non-GT registers (e.g., > display). However since these later platforms also introduce media > engines at higher MMIO offsets, the definition of NEEDS_FORCE_WAKE() is > extended to also consider register offsets above GEN11_BSD_RING_BASE. > > v2: > - Restore NEEDS_FORCE_WAKE(), but extend it for compatibility with the > gen11+ platforms by also passing offsets above GEN11_BSD_RING_BASE. > (Chris, Tvrtko) > > Cc: Tvrtko Ursulin > Cc: Chris Wilson > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/intel_uncore.c | 61 ++++++++++------------------- > 1 file changed, 21 insertions(+), 40 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 4c6898746d10..bfb2a6337f9d 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -851,7 +851,10 @@ void assert_forcewakes_active(struct intel_uncore *uncore, > } > > /* We give fast paths for the really cool registers */ > -#define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) > +#define NEEDS_FORCE_WAKE(reg) ({ \ > + u32 __reg = (reg); \ > + __reg < 0x40000 || __reg >= GEN11_BSD_RING_BASE; \ > +}) > > static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry) > { > @@ -1071,27 +1074,10 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = { > }; > > #define __fwtable_reg_write_fw_domains(uncore, offset) \ > -({ \ > - enum forcewake_domains __fwd = 0; \ > - if (NEEDS_FORCE_WAKE((offset)) && !is_shadowed(uncore, offset)) \ > - __fwd = find_fw_domain(uncore, offset); \ > - __fwd; \ > -}) > - > -#define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \ > ({ \ > enum forcewake_domains __fwd = 0; \ > const u32 __offset = (offset); \ > - if (!is_shadowed(uncore, __offset)) \ > - __fwd = find_fw_domain(uncore, __offset); \ > - __fwd; \ > -}) > - > -#define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \ > -({ \ > - enum forcewake_domains __fwd = 0; \ > - const u32 __offset = (offset); \ > - if (!is_shadowed(uncore, __offset)) \ > + if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \ > __fwd = find_fw_domain(uncore, __offset); \ > __fwd; \ > }) > @@ -1675,34 +1661,29 @@ __gen6_write(8) > __gen6_write(16) > __gen6_write(32) > > -#define __gen_write(func, x) \ > +#define __gen_fwtable_write(x) \ > static void \ > -func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ > +fwtable_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ > enum forcewake_domains fw_engine; \ > GEN6_WRITE_HEADER; \ > - fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \ > + fw_engine = __fwtable_reg_write_fw_domains(uncore, offset); \ > if (fw_engine) \ > __force_wake_auto(uncore, fw_engine); \ > __raw_uncore_write##x(uncore, reg, val); \ > GEN6_WRITE_FOOTER; \ > } > > -#define __gen_reg_write_funcs(func) \ > -static enum forcewake_domains \ > -func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ > - return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ > -} \ > -\ > -__gen_write(func, 8) \ > -__gen_write(func, 16) \ > -__gen_write(func, 32) > - > +static enum forcewake_domains > +fwtable_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) > +{ > + return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); > +} > > -__gen_reg_write_funcs(gen12_fwtable); > -__gen_reg_write_funcs(gen11_fwtable); > -__gen_reg_write_funcs(fwtable); > +__gen_fwtable_write(8) > +__gen_fwtable_write(16) > +__gen_fwtable_write(32) > > -#undef __gen_reg_write_funcs > +#undef __gen_fwtable_write > #undef GEN6_WRITE_FOOTER > #undef GEN6_WRITE_HEADER > > @@ -2080,22 +2061,22 @@ static int uncore_forcewake_init(struct intel_uncore *uncore) > if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { > ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges); > ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs); > - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable); > + ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); > ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); > } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { > ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges); > ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs); > - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable); > + ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); > ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); > } else if (GRAPHICS_VER(i915) >= 12) { > ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges); > ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs); > - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable); > + ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); > ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); > } else if (GRAPHICS_VER(i915) == 11) { > ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges); > ASSIGN_SHADOW_TABLE(uncore, gen11_shadowed_regs); > - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable); > + ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); > ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); > } else if (IS_GRAPHICS_VER(i915, 9, 10)) { > ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges); > Reviewed-by: Tvrtko Ursulin Regards, Tvrtko