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d="scan'208";a="182182675" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.100]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2025 08:00:54 -0700 From: Jani Nikula To: Gustavo Sousa , intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Ankit Nautiyal , Dnyaneshwar Bhadane , Gustavo Sousa , Jouni =?utf-8?Q?H=C3=B6gander?= , Juha-pekka Heikkila , Luca Coelho , Lucas De Marchi , Matt Atwood , Matt Roper , Ravi Kumar Vodapalli , Sai Teja Pottumuttu , Shekhar Chauhan , Vinod Govindapillai Subject: Re: [PATCH 19/32] drm/i915/xe3p_lpd: PSR SU minimum lines is 4 In-Reply-To: <20251015-xe3p_lpd-basic-enabling-v1-19-d2d1e26520aa@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20251015-xe3p_lpd-basic-enabling-v1-0-d2d1e26520aa@intel.com> <20251015-xe3p_lpd-basic-enabling-v1-19-d2d1e26520aa@intel.com> Date: Wed, 15 Oct 2025 18:00:51 +0300 Message-ID: <9437c341d8a7ce4104ca3b65275f34ea728259db@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 15 Oct 2025, Gustavo Sousa wrote: > From: Jouni H=C3=B6gander > > Ensure the minimum selective update line count is 4 in case of display > version 35 and onwards. > > Bspec: 69887 > Signed-off-by: Jouni H=C3=B6gander > Signed-off-by: Gustavo Sousa > --- > drivers/gpu/drm/i915/display/intel_psr.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i= 915/display/intel_psr.c > index 2131473cead6..c663ca91f490 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -2701,6 +2701,29 @@ intel_psr_apply_su_area_workarounds(struct intel_c= rtc_state *crtc_state) > intel_psr_apply_pr_link_on_su_wa(crtc_state); > } >=20=20 > +static void intel_psr_su_area_min_lines(struct intel_crtc_state *crtc_st= ate) > +{ > + struct intel_display *display =3D to_intel_display(crtc_state); > + struct drm_rect damaged_area; > + > + /* > + * Bspec mentions 4 being minimum lines in SU for display version > + * 35 and onwards. > + */ > + if (DISPLAY_VER(display) < 35 || drm_rect_height(&crtc_state->psr2_su_a= rea) >=3D 4) > + return; > + > + damaged_area.x1 =3D crtc_state->psr2_su_area.x1; > + damaged_area.y1 =3D crtc_state->psr2_su_area.y1; > + damaged_area.x2 =3D crtc_state->psr2_su_area.x2; > + damaged_area.y2 =3D crtc_state->psr2_su_area.y2; > + > + damaged_area.y2 +=3D 4 - drm_rect_height(&damaged_area); > + drm_rect_intersect(&damaged_area, &crtc_state->pipe_src); > + damaged_area.y1 -=3D 4 - drm_rect_height(&damaged_area); Stray extra spaces in there. > + clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state-= >pipe_src); > +} > + > int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, > struct intel_crtc *crtc) > { > @@ -2809,6 +2832,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic= _state *state, > if (full_update) > goto skip_sel_fetch_set_loop; >=20=20 > + intel_psr_su_area_min_lines(crtc_state); > + > intel_psr_apply_su_area_workarounds(crtc_state); >=20=20 > ret =3D drm_atomic_add_affected_planes(&state->base, &crtc->base); --=20 Jani Nikula, Intel