From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B99EC79F80 for ; Fri, 4 Sep 2026 07:10:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05DBC10E13B; Fri, 4 Sep 2026 07:10:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="g/giY1B3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 918A410E13B; Fri, 4 Sep 2026 07:10:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788505839; x=1820041839; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version; bh=WqmuqwKQnF/E5rxeOPBqmJpNR7Vf1Bx2BKzlO3uTG2o=; b=g/giY1B3wKptEvjekIpazgptey5aKeH9GNpt+ze9wgUGnKVM4kTeprRD kPXGiMo5CUX5zP81tnQdxXKCOHNbEQEYNycJaKLpaPfyb+mS3MDirJOoR zD1tRNhnNGAWUfknyeKBxtQqy0+pXYAoktw3hoypt/0r56yjltR6Zy632 tyWNd6eVMgjI/zOCI+H/5EhxB8PsnjYZynr4M0nRuS65H7YoGzeRhGwpr StfiO+Ajq3DVkAfRjMqSUGiSKwX4ZiXz+/x5EMFW2AI132ZuD8gwNo+Dh 2XB5MIxsLdDJW9/WUccy+sqrD9eV8UaqUOkeVOCcsAdutaTChkBidMPb4 Q==; X-CSE-ConnectionGUID: IKnUEByzQVae0uLSlmRXuQ== X-CSE-MsgGUID: 44dI2Dx+SFqjPGV/A2IW5w== X-IronPort-AV: E=McAfee;i="6800,10657,11895"; a="76557210" X-IronPort-AV: E=Sophos;i="6.25,260,1779174000"; d="scan'208";a="76557210" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Sep 2026 00:10:39 -0700 X-CSE-ConnectionGUID: cZI28kdARfS5he5rr/BvQA== X-CSE-MsgGUID: zKAucWnhSIGMOHjuv7TBLA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,260,1779174000"; d="scan'208";a="265616271" Received: from amilburn-desk.amilburn-desk (HELO localhost) ([10.245.244.170]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Sep 2026 00:10:37 -0700 From: Jani Nikula To: Nemesa Garg , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Nemesa Garg Subject: Re: [PATCH] drm/i915/display: Limit SEL_FETCH clear to supported pipes In-Reply-To: <20260904062744.3010375-1-nemesa.garg@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland References: <20260904062744.3010375-1-nemesa.garg@intel.com> Date: Fri, 04 Sep 2026 10:10:34 +0300 Message-ID: <9514a15f9ded3fa79572f92a61f33650c4ab02e6@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 04 Sep 2026, Nemesa Garg wrote: > Commit 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL > on plane disable") started clearing SEL_FETCH_PLANE_CTL and > SEL_FETCH_CUR_CTL on every plane and cursor disable. > > Not all pipes implement these registers. Clearing them on a pipe > that does not have them leads to an unclaimed register access. Where are the corresponding checks on the enable side, and what prevented this before 7f1172a2ac0d? BR, Jani. > > Skip the clear on pipes that do not implement the registers. > > Fixes: 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL on plane disable") > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16876 > Assisted-by: GitHub-Copilot:claude-opus-4.6 > Signed-off-by: Nemesa Garg > --- > drivers/gpu/drm/i915/display/intel_cursor.c | 4 ++++ > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c > index 86bb96ac449b..3c06d5482691 100644 > --- a/drivers/gpu/drm/i915/display/intel_cursor.c > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c > @@ -544,6 +544,10 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb, > if (!HAS_PSR2_SEL_FETCH(display)) > return; > > + /* Display ver 12 only instantiates these registers for pipe A */ > + if (DISPLAY_VER(display) == 12 && pipe != PIPE_A) > + return; > + > intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0); > } > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index 5cda1ab90e40..252df30debc9 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -893,6 +893,10 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb, > if (!HAS_PSR2_SEL_FETCH(display)) > return; > > + /* Display ver 12 only instantiates these registers for pipe A */ > + if (DISPLAY_VER(display) == 12 && pipe != PIPE_A) > + return; > + > intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0); > } -- Jani Nikula, Intel