From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1E0CC433F5 for ; Wed, 13 Oct 2021 14:39:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5C8AC610E5 for ; Wed, 13 Oct 2021 14:39:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5C8AC610E5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B5DA36E069; Wed, 13 Oct 2021 14:39:52 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id E76326E069; Wed, 13 Oct 2021 14:39:51 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10135"; a="227400841" X-IronPort-AV: E=Sophos;i="5.85,371,1624345200"; d="scan'208";a="227400841" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2021 07:39:51 -0700 X-IronPort-AV: E=Sophos;i="5.85,371,1624345200"; d="scan'208";a="524653403" Received: from lapeders-mobl.ger.corp.intel.com (HELO [10.249.254.46]) ([10.249.254.46]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2021 07:39:50 -0700 Message-ID: <95bf4577-ea21-0995-3bc7-2588fa92debf@linux.intel.com> Date: Wed, 13 Oct 2021 16:39:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.1.0 Content-Language: en-US To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, maarten.lankhorst@linux.intel.com, matthew.auld@intel.com References: <20211008133530.664509-1-thomas.hellstrom@linux.intel.com> <20211008133530.664509-5-thomas.hellstrom@linux.intel.com> <3af6691caadc315b01bf3acdff94ff14f967a4a4.camel@linux.intel.com> From: =?UTF-8?Q?Thomas_Hellstr=c3=b6m?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add a struct dma_fence_work timeline X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 10/13/21 16:33, Daniel Vetter wrote: > On Wed, Oct 13, 2021 at 04:21:43PM +0200, Thomas Hellström wrote: >> On Wed, 2021-10-13 at 14:43 +0200, Daniel Vetter wrote: >>> On Fri, Oct 08, 2021 at 03:35:28PM +0200, Thomas Hellström wrote: >>>> The TTM managers and, possibly, the gtt address space managers will >>>> need to be able to order fences for async operation. >>>> Using dma_fence_is_later() for this will require that the fences we >>>> hand >>>> them are from a single fence context and ordered. >>>> >>>> Introduce a struct dma_fence_work_timeline, and a function to >>>> attach >>>> struct dma_fence_work to such a timeline in a way that all previous >>>> fences attached to the timeline will be signaled when the latest >>>> attached struct dma_fence_work signals. >>>> >>>> Signed-off-by: Thomas Hellström >>> I'm not understanding why we need this: >>> >>> - if we just want to order dma_fence work, then an ordered workqueue >>> is >>>   what we want. Which is why hand-rolling is better than reusing >>>   dma_fence_work for absolutely everything. >>> >>> - if we just need to make sure the public fences signal in order, >>> then >>>   it's a dma_fence_chain. >> Part of the same series that needs reworking. >> >> What we need here is a way to coalesce multiple fences from various >> contexts (including both gpu and work fences) into a single fence and >> then attach it to a timeline. > I thought dma_fence_chain does this for you, including coelescing on the > same timeline. Or at least it's supposed to, because if it doesn't you can > produce some rather epic chain explosions with vulkan :-) I'll take a look to see if I can use dma_fence_chain for this case. Thanks, /Thomas > -Daniel