From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDF5AC433EF for ; Wed, 1 Jun 2022 12:30:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2D10210E8B8; Wed, 1 Jun 2022 12:30:19 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 90CA510E2E8; Wed, 1 Jun 2022 12:30:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654086617; x=1685622617; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=lGj1AD0mBETr8eVn06GPE/82cfs7g+EbDCQL1mvPf1c=; b=cM3LnfFTDhOGZgKYROzrGp9ar0k71mZfpy5d9YOe5bnC0UMxojMzS3dx 4uXjhCo1FrovO1xwfozrAn+6OvjAAguYavb5uRL44iReBthhY5gNduVKZ Zh9LH2mF9V/MSDLkxssN5P6U7HCwOKVdW73klFUUVDmK+pIkSNUz0qurq jEMHx/8PL1IgXvGM45S0+WCVxmnHAzjTQoLpKWYJSnfBZX7R0dLxv2kpB bLdm0bd3PrkP5dsSmEIYqyQjttBdb2BMNqe3+cJLTleXFL0N+rdverOBk TFiEq7ZMqj8M0Fs8p/lCZ0u/BrnxgCPf32P6mofO7QO+DVr68B4baMG4u Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10364"; a="338614517" X-IronPort-AV: E=Sophos;i="5.91,268,1647327600"; d="scan'208";a="338614517" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2022 05:30:17 -0700 X-IronPort-AV: E=Sophos;i="5.91,268,1647327600"; d="scan'208";a="576912086" Received: from nirmoyda-mobl.ger.corp.intel.com (HELO [10.251.213.124]) ([10.251.213.124]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2022 05:30:15 -0700 Message-ID: <9a37b6f6-b540-7b5e-ce07-25e358016231@linux.intel.com> Date: Wed, 1 Jun 2022 14:30:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Content-Language: en-US To: Matthew Auld , intel-gfx@lists.freedesktop.org References: <20220525184337.491763-1-matthew.auld@intel.com> <20220525184337.491763-7-matthew.auld@intel.com> From: "Das, Nirmoy" In-Reply-To: <20220525184337.491763-7-matthew.auld@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [Intel-gfx] [PATCH 06/10] drm/i915/uapi: add NEEDS_CPU_ACCESS hint X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Thomas_Hellstr=c3=b6m?= , Kenneth Graunke , dri-devel@lists.freedesktop.org, Daniel Vetter Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" LGTM Reviewed-by: Nirmoy Das On 5/25/2022 8:43 PM, Matthew Auld wrote: > If set, force the allocation to be placed in the mappable portion of > I915_MEMORY_CLASS_DEVICE. One big restriction here is that system memory > (i.e I915_MEMORY_CLASS_SYSTEM) must be given as a potential placement for the > object, that way we can always spill the object into system memory if we > can't make space. > > Testcase: igt@gem-create@create-ext-cpu-access-sanity-check > Testcase: igt@gem-create@create-ext-cpu-access-big > Signed-off-by: Matthew Auld > Cc: Thomas Hellström > Cc: Lionel Landwerlin > Cc: Jon Bloomfield > Cc: Daniel Vetter > Cc: Jordan Justen > Cc: Kenneth Graunke > Cc: Akeem G Abodunrin > --- > drivers/gpu/drm/i915/gem/i915_gem_create.c | 26 ++++++--- > include/uapi/drm/i915_drm.h | 61 +++++++++++++++++++--- > 2 files changed, 71 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c > index d094cae0ddf1..33673fe7ee0a 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c > @@ -241,6 +241,7 @@ struct create_ext { > struct drm_i915_private *i915; > struct intel_memory_region *placements[INTEL_REGION_UNKNOWN]; > unsigned int n_placements; > + unsigned int placement_mask; > unsigned long flags; > }; > > @@ -337,6 +338,7 @@ static int set_placements(struct drm_i915_gem_create_ext_memory_regions *args, > for (i = 0; i < args->num_regions; i++) > ext_data->placements[i] = placements[i]; > > + ext_data->placement_mask = mask; > return 0; > > out_dump: > @@ -411,7 +413,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, > struct drm_i915_gem_object *obj; > int ret; > > - if (args->flags) > + if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS) > return -EINVAL; > > ret = i915_user_extensions(u64_to_user_ptr(args->extensions), > @@ -427,13 +429,21 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, > ext_data.n_placements = 1; > } > > - /* > - * TODO: add a userspace hint to force CPU_ACCESS for the object, which > - * can override this. > - */ > - if (ext_data.n_placements > 1 || > - ext_data.placements[0]->type != INTEL_MEMORY_SYSTEM) > - ext_data.flags |= I915_BO_ALLOC_GPU_ONLY; > + if (args->flags & I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS) { > + if (ext_data.n_placements == 1) > + return -EINVAL; > + > + /* > + * We always need to be able to spill to system memory, if we > + * can't place in the mappable part of LMEM. > + */ > + if (!(ext_data.placement_mask & BIT(INTEL_REGION_SMEM))) > + return -EINVAL; > + } else { > + if (ext_data.n_placements > 1 || > + ext_data.placements[0]->type != INTEL_MEMORY_SYSTEM) > + ext_data.flags |= I915_BO_ALLOC_GPU_ONLY; > + } > > obj = __i915_gem_object_create_user_ext(i915, args->size, > ext_data.placements, > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index e30f31a440b3..5b0a10e6a1b8 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -3366,11 +3366,11 @@ struct drm_i915_query_memory_regions { > * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added > * extension support using struct i915_user_extension. > * > - * Note that in the future we want to have our buffer flags here, at least for > - * the stuff that is immutable. Previously we would have two ioctls, one to > - * create the object with gem_create, and another to apply various parameters, > - * however this creates some ambiguity for the params which are considered > - * immutable. Also in general we're phasing out the various SET/GET ioctls. > + * Note that new buffer flags should be added here, at least for the stuff that > + * is immutable. Previously we would have two ioctls, one to create the object > + * with gem_create, and another to apply various parameters, however this > + * creates some ambiguity for the params which are considered immutable. Also in > + * general we're phasing out the various SET/GET ioctls. > */ > struct drm_i915_gem_create_ext { > /** > @@ -3378,7 +3378,6 @@ struct drm_i915_gem_create_ext { > * > * The (page-aligned) allocated size for the object will be returned. > * > - * > * DG2 64K min page size implications: > * > * On discrete platforms, starting from DG2, we have to contend with GTT > @@ -3390,7 +3389,9 @@ struct drm_i915_gem_create_ext { > * > * Note that the returned size here will always reflect any required > * rounding up done by the kernel, i.e 4K will now become 64K on devices > - * such as DG2. > + * such as DG2. The kernel will always select the largest minimum > + * page-size for the set of possible placements as the value to use when > + * rounding up the @size. > * > * Special DG2 GTT address alignment requirement: > * > @@ -3414,14 +3415,58 @@ struct drm_i915_gem_create_ext { > * is deemed to be a good compromise. > */ > __u64 size; > + > /** > * @handle: Returned handle for the object. > * > * Object handles are nonzero. > */ > __u32 handle; > - /** @flags: MBZ */ > + > + /** > + * @flags: Optional flags. > + * > + * Supported values: > + * > + * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that > + * the object will need to be accessed via the CPU. > + * > + * Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only > + * strictly required on configurations where some subset of the device > + * memory is directly visible/mappable through the CPU (which we also > + * call small BAR), like on some DG2+ systems. Note that this is quite > + * undesirable, but due to various factors like the client CPU, BIOS etc > + * it's something we can expect to see in the wild. See > + * &drm_i915_memory_region_info.probed_cpu_visible_size for how to > + * determine if this system applies. > + * > + * Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to > + * ensure the kernel can always spill the allocation to system memory, > + * if the object can't be allocated in the mappable part of > + * I915_MEMORY_CLASS_DEVICE. > + * > + * Also note that since the kernel only supports flat-CCS on objects > + * that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore > + * don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with > + * flat-CCS. > + * > + * Without this hint, the kernel will assume that non-mappable > + * I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the > + * kernel can still migrate the object to the mappable part, as a last > + * resort, if userspace ever CPU faults this object, but this might be > + * expensive, and so ideally should be avoided. > + * > + * On older kernels which lack the relevant small-bar uAPI support (see > + * also &drm_i915_memory_region_info.probed_cpu_visible_size), > + * usage of the flag will result in an error, but it should NEVER be > + * possible to end up with a small BAR configuration, assuming we can > + * also successfully load the i915 kernel module. In such cases the > + * entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as > + * such there are zero restrictions on where the object can be placed. > + */ > +#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0) > __u32 flags; > + > /** > * @extensions: The chain of extensions to apply to this object. > *