From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88D46C004C0 for ; Mon, 23 Oct 2023 15:24:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1DAFD10E214; Mon, 23 Oct 2023 15:24:53 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id DC57F10E214 for ; Mon, 23 Oct 2023 15:24:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698074690; x=1729610690; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=qycrxZCkMH/BZX8chUcR0a+GuxsVdac5Dot0a+h81+Y=; b=RlVL2TTDeG7JPPjf3y5AiIAsG7N6kZYfCYHMFUnrX+zbIad1TxSi7AoB dvtETzQhCZxk3ItbemyO72pTfmMuLglxNvw4yhyWt4ZR7mT+IvWxz5uxZ q07HaPc9SlT71piyBsPiL7bYROLw6MuB5V0zI3JQD5kggCahNgUdj02Bv zddFtCkNJLS/Rg5pj3k2gmtO7B7ZPsWouAI3wIpfxrXTuEKApQaKzWoQo w55Q01LsRzkgRLPeH65qeZTs5tWYn5WJHPBtZ2zfpVG2fmmskwAFVqBz6 k8RTUzJZ53kqlgxm8XYjiL3U/e/ozC2g7EiVh3z8tMKORwez4VESdjvWp w==; X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="366208531" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="366208531" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 08:24:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="874731406" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="874731406" Received: from ahajda-mobl.ger.corp.intel.com (HELO [10.213.1.152]) ([10.213.1.152]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 08:24:48 -0700 Message-ID: <9e296a17-5a7a-473d-a213-a1e965a3dc4a@intel.com> Date: Mon, 23 Oct 2023 17:24:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: Nirmoy Das , intel-gfx@lists.freedesktop.org References: <20231023-wabb-v3-0-1a4fbc632440@intel.com> <20231023-wabb-v3-4-1a4fbc632440@intel.com> <7a83d52f-0bcb-6223-db6c-1bf9cb7ed39b@linux.intel.com> From: Andrzej Hajda Organization: Intel Technology Poland sp. z o.o. - ul. Slowackiego 173, 80-298 Gdansk - KRS 101882 - NIP 957-07-52-316 In-Reply-To: <7a83d52f-0bcb-6223-db6c-1bf9cb7ed39b@linux.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [Intel-gfx] [PATCH v3 4/4] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Cavitt , Nirmoy Das Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 23.10.2023 11:55, Nirmoy Das wrote: > Hi Andrzej, > > On 10/23/2023 9:41 AM, Andrzej Hajda wrote: >> From: Jonathan Cavitt >> >> Set copy engine arbitration into round robin mode >> for part of Wa_16018031267 / Wa_16018063123 mitigation. >> >> Signed-off-by: Nirmoy Das >> Signed-off-by: Jonathan Cavitt >> Reviewed-by: Andrzej Hajda >> --- >>   drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++ >>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ >>   2 files changed, 8 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h >> b/drivers/gpu/drm/i915/gt/intel_engine_regs.h >> index b8618ee3e3041a..c0c8c12edea104 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h >> @@ -124,6 +124,9 @@ >>   #define RING_INDIRECT_CTX(base)            _MMIO((base) + 0x1c4) /* >> gen8+ */ >>   #define RING_INDIRECT_CTX_OFFSET(base)        _MMIO((base) + 0x1c8) >> /* gen8+ */ >>   #define ECOSKPD(base)                _MMIO((base) + 0x1d0) >> +#define   XEHP_BLITTER_SCHEDULING_MODE_MASK    REG_GENMASK(12, 11) >> +#define   XEHP_BLITTER_ROUND_ROBIN_MODE        \ >> +        REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1) >>   #define   ECO_CONSTANT_BUFFER_SR_DISABLE    REG_BIT(4) >>   #define   ECO_GATING_CX_ONLY            REG_BIT(3) >>   #define   GEN6_BLITTER_FBC_NOTIFY        REG_BIT(3) >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> index 192ac0e59afa13..108d9326735910 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> @@ -2782,6 +2782,11 @@ xcs_engine_wa_init(struct intel_engine_cs >> *engine, struct i915_wa_list *wal) >>                RING_SEMA_WAIT_POLL(engine->mmio_base), >>                1); >>       } >> +    /* Wa_16018031267, Wa_16018063123 */ >> +    if (NEEDS_FASTCOLOR_BLT_WABB(engine)) > > > Not sure if I missed any previous discussion on this, the WA talked > about applying this on main copy engine. This needs to be taken into > account in > > NEEDS_FASTCOLOR_BLT_WABB() Do you mean we need to check if instance == 0? Now above macro checks if it is copy engine. > >> +        wa_masked_field_set(wal, ECOSKPD(engine->mmio_base), >> +                    XEHP_BLITTER_SCHEDULING_MODE_MASK, >> +                    XEHP_BLITTER_ROUND_ROBIN_MODE); >>   } > > This function sets masked_reg = true and will not read the register back > and I remember MattR asked internally to not use that if that is not > required. IIRC, wa_masked_field_set sets read_mask, so read back is performed, anyway it is the only function (beside low level wa_add), which works on fields(not bits). Are you sure? Regards Andrzej > > > With those two concern handled this is  Reviewed-by: Nirmoy Das > > > > Regards, > > Nirmoy > >>   static void >>