Re: [Intel-gfx] [PATCH 0/2] PL1 power limit fixes for ATSM

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Thu, Feb 16, 2023 at 08:49:42AM -0800, Ashutosh Dixit wrote:
> Previous PL1 power limit implementation assumed that the PL1 limit is
> always enabled in HW. However we now find this not to be the case on ATSM
> where the PL1 limit is disabled at power up. This requires changes in the
> previous PL1 limit implementation.
> 
> v2: Dropping Patch 3 (since it is NAK'd by hwmon) so that the first two
>     patches can get merged. The first two patches are sufficient to fix the
>     main ATSM issue.

pushed both patches to drm-intel-next.

> 
> Ashutosh Dixit (2):
>   drm/i915/hwmon: Replace hwm_field_scale_and_write with
>     hwm_power_max_write
>   drm/i915/hwmon: Enable PL1 limit when writing limit value to HW
> 
>  drivers/gpu/drm/i915/i915_hwmon.c | 37 ++++++++++++++-----------------
>  1 file changed, 17 insertions(+), 20 deletions(-)
> 
> -- 
> 2.38.0
>