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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 09/12] drm/i915: Define transcoder timing register bitmasks
Date: Tue, 14 Feb 2023 12:57:18 +0200	[thread overview]
Message-ID: <Y+tpDkV+/PtK0nKX@intel.com> (raw)
In-Reply-To: <875yc4tu3y.fsf@intel.com>

On Tue, Feb 14, 2023 at 12:32:49PM +0200, Jani Nikula wrote:
> On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> > index ef0c7f5b0ad6..8f2ebead0826 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> > @@ -698,11 +698,11 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> >  	save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
> >  	vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
> >  
> > -	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
> > -	vactive = (save_vtotal & 0x7ff) + 1;
> > +	vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
> > +	vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
> >  
> > -	vblank_start = (vblank & 0xfff) + 1;
> > -	vblank_end = ((vblank >> 16) & 0xfff) + 1;
> > +	vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;
> > +	vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
> 
> I forget how these are defined in bspec and if the field size grows
> towards later platforms... but this widens the masks. I'm guess it'll
> probably read as zero anyway, but in theory that's a functional change.

Missed the fact tht this used smaller masks here for these few.
But it should be all good as eveywhere else we've been using the
full 16bits, so the state checker should have spotted any extra
garbage in the high bits.

But I'll add a note to the commit message, just in case.

-- 
Ville Syrjälä
Intel

  parent reply	other threads:[~2023-02-14 10:57 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 01/12] drm/i915: Rename intel_ddi_{enable, disable}_pipe_clock() Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 02/12] drm/i915: Flatten intel_ddi_{enable, disable}_transcoder_clock() Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 03/12] drm/i915: Give CPU transcoder timing registers TRANS_ prefix Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 04/12] drm/i915: s/PIPECONF/TRANSCONF/ Ville Syrjala
2023-02-14 10:05   ` Jani Nikula
2023-02-14 10:32     ` Ville Syrjälä
2023-02-14 10:52       ` Jani Nikula
2023-02-14 10:59         ` Ville Syrjälä
2023-02-13 22:52 ` [Intel-gfx] [PATCH 05/12] drm/i915: Dump blanking start/end Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 06/12] drm/i915: Define the "unmodified vblank" interrupt bit Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 07/12] drm/i915/psr: Stop clobbering TRANS_SET_CONTEXT_LATENCY Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 08/12] drm/i915: Add local adjusted_mode variable Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 09/12] drm/i915: Define transcoder timing register bitmasks Ville Syrjala
2023-02-14 10:32   ` Jani Nikula
2023-02-14 10:34     ` Jani Nikula
2023-02-14 10:57     ` Ville Syrjälä [this message]
2023-02-13 22:52 ` [Intel-gfx] [PATCH 10/12] drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+ Ville Syrjala
2023-02-16 14:28   ` Jani Nikula
2023-02-13 22:52 ` [Intel-gfx] [PATCH 11/12] drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess Ville Syrjala
2023-02-14 10:35   ` Jani Nikula
2023-02-20 21:29   ` Ville Syrjälä
2023-02-13 22:52 ` [Intel-gfx] [PATCH 12/12] drm/i915: Remove pointless register read Ville Syrjala
2023-02-14 10:38   ` Jani Nikula
2023-02-13 23:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Transcoder timing stuff Patchwork
2023-02-13 23:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-02-14  2:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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