From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 04/12] drm/i915: s/PIPECONF/TRANSCONF/
Date: Tue, 14 Feb 2023 12:59:55 +0200 [thread overview]
Message-ID: <Y+tpq7S3tGIeEen6@intel.com> (raw)
In-Reply-To: <87r0ussem9.fsf@intel.com>
On Tue, Feb 14, 2023 at 12:52:46PM +0200, Jani Nikula wrote:
> On Tue, 14 Feb 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Tue, Feb 14, 2023 at 12:05:33PM +0200, Jani Nikula wrote:
> >> On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> >> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >
> >> > Rename PIPECONF to TRANSCONF to make it clear what it actually
> >> > applies to.
> >> >
> >> > While the usual convention is to pick the earliers name I think
> >> > in this case it's more clear to use the later name. Especially
> >> > as even the register offset is in the wrong range (0x70000 vs.
> >> > 0x60000) and thus makes it look like this is per-pipe.
> >> >
> >> > There is one place in gvt that's doing something with TRANSCONF
> >> > while iterating with for_each_pipe(). So that might not be doing
> >> > the right thing for TRANSCODER_EDP, dunno. Not knowing what it
> >> > does I left it as is to avoid breakage.
> >>
> >> I recently looked at _PIPE_EDP usage, and thought all of it looked a bit
> >> suspect, but didn't bother to dig deeper. Maybe after this it could be
> >> removed?
> >
> > I think it needs to stay due to the pipe_offsets[] stuff
> > and hw making a mess of pipe vs. transcoder registers.
> > But no one should really use it anywhere else.
>
> I wonder how many underscores more we need to add to keep it that
> way. :p
People are probably accustomed to one or two. So maybe three?
Could also try adding a comment, but dunno if it would any
more effective.
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2023-02-14 11:00 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 01/12] drm/i915: Rename intel_ddi_{enable, disable}_pipe_clock() Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 02/12] drm/i915: Flatten intel_ddi_{enable, disable}_transcoder_clock() Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 03/12] drm/i915: Give CPU transcoder timing registers TRANS_ prefix Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 04/12] drm/i915: s/PIPECONF/TRANSCONF/ Ville Syrjala
2023-02-14 10:05 ` Jani Nikula
2023-02-14 10:32 ` Ville Syrjälä
2023-02-14 10:52 ` Jani Nikula
2023-02-14 10:59 ` Ville Syrjälä [this message]
2023-02-13 22:52 ` [Intel-gfx] [PATCH 05/12] drm/i915: Dump blanking start/end Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 06/12] drm/i915: Define the "unmodified vblank" interrupt bit Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 07/12] drm/i915/psr: Stop clobbering TRANS_SET_CONTEXT_LATENCY Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 08/12] drm/i915: Add local adjusted_mode variable Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 09/12] drm/i915: Define transcoder timing register bitmasks Ville Syrjala
2023-02-14 10:32 ` Jani Nikula
2023-02-14 10:34 ` Jani Nikula
2023-02-14 10:57 ` Ville Syrjälä
2023-02-13 22:52 ` [Intel-gfx] [PATCH 10/12] drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+ Ville Syrjala
2023-02-16 14:28 ` Jani Nikula
2023-02-13 22:52 ` [Intel-gfx] [PATCH 11/12] drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess Ville Syrjala
2023-02-14 10:35 ` Jani Nikula
2023-02-20 21:29 ` Ville Syrjälä
2023-02-13 22:52 ` [Intel-gfx] [PATCH 12/12] drm/i915: Remove pointless register read Ville Syrjala
2023-02-14 10:38 ` Jani Nikula
2023-02-13 23:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Transcoder timing stuff Patchwork
2023-02-13 23:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-02-14 2:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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