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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?/okkwcGxAQ8+y0ugYemKBB/q+XVmoNY81EJIvV3IR6XNvRhJEgcydgfLNM2X?= =?us-ascii?Q?npOkaim4z0GeUKZAEzIh30YYM4kqvhtC24dDkbxuzSwyMvXmglIj/EJXWmDm?= =?us-ascii?Q?E+Ry3BWwoUb24He+DDKwApmiDaUCryQBOpdaX2lYL874TkpeXhjxsrZrlG87?= =?us-ascii?Q?DzrylGkIIm1yjAoLHzM+10OwunMCjyNXJ6jdLZw0g//+/eI/vS9voBcvQtaJ?= =?us-ascii?Q?Ls3jGaDLpY5bU5PM86CcCrkhb1nSeTbMUCxuhXYM1q89jcQxFLTjF+Krp48X?= =?us-ascii?Q?y1r7dPsc3wR/4Js9dcfl2ba5OL/eKleEDdS7qtu8UdXvB5Og5nYzHko+osmU?= =?us-ascii?Q?zen+IpKLNrPOoiNLMJfCUCvVpe5NQr5yv7gpEcbu+4mkZ7HrOm/rjMRcj3qe?= =?us-ascii?Q?lBUQXoSPt8QQLzd4Ley0Ei+bi8Q8KrhVhNQNxGwLUfL1DJfvhisQE9WkzpVZ?= =?us-ascii?Q?C0rkjKmkTlWGUT1Y3xiOpl1H7NHns8BtOt7Vm/yI7sMsb4VeNauXr2AJDz8a?= =?us-ascii?Q?rJFfAp4P4yfgVIWyrVxl9uyRDWxjtb7EH1iQHhrmfrerxsbKxTgAQygB/4ou?= =?us-ascii?Q?5vrDrUBPTog1YMiu4ufhoa2wyvV1cE6cqD+HI5j1OImR0dLi+tR291MgXJnK?= =?us-ascii?Q?dOBW9tKHWq8bid7lDsuUuW6q/nlEpNH/ESQKdDw6R6LB9msNx2dwI67UtrZG?= =?us-ascii?Q?28bzficmX8BKcMep5KdtgxntZIdfUqxXb38TnPxiScYPKvsY6/3Cnht550I3?= =?us-ascii?Q?msQzdI9Bm4qJjwIVm6yCjsjv3Sf2Qb8GurLtvLzDMBnwqBALDrRBPAJASOHo?= =?us-ascii?Q?eIsdJT2dDAKXQaTwgQK38hMRlDB8Nw99/t37OUGS+eqC+1ZWlRUqXHDEb48B?= =?us-ascii?Q?uCvobn4cXl8hkRKWEwW2lSw6xeug3iu8oUZotfQoSvv2fLPlex/3SveK+Z3Y?= =?us-ascii?Q?WMIIZdnV/f0PM5GbaLPVEoy8mO0L5kEZCPJmlAkrEmMyn+S/W6ibvERJnd+x?= =?us-ascii?Q?JAp0MFYuOHhWjfv0kwwtuREHpUbFDMgtvfsIhdbIdq/cjA5dHPLaC1aTvYsO?= =?us-ascii?Q?x0ciwgPvjOhmcs/EkdjLXcJBTOKxO0grAg9fh634f31i4iuex9DqPzzHuuAK?= =?us-ascii?Q?Cew5bkp4aKqdPdwxL963aJeMU7yQ/csEM14T+5yRIQrYTG+I7vn8nPgNab2I?= =?us-ascii?Q?Q3VWxuTObL7B/09vt7Utka/jzFSS4J68BsKNzHllb2D8zJGh/FeVCjjaQgAy?= =?us-ascii?Q?2Nq+GjY6XAxY6+xsu0LowgI1A0PUANNOhoQACWPlLyM5pWRtbxunG4Aj8sRM?= =?us-ascii?Q?iF5WfmNR46tBKMLFzXeBYcU+9Tsido2I/JAhKgI3uDFPN1NLLR2o68zZ/Dyh?= =?us-ascii?Q?Ef3LSOS+Ut5YzlvIpdpblKV4w9VyMdY+IxX3WoGhqXmoBWX95VH98eiNGilp?= =?us-ascii?Q?7i4t5Kso0Fk3ZRKLKu9fOwLZkz4ZB4teqQwwagDJxQ332QHO/OXnjEe5ejC5?= =?us-ascii?Q?XPg00/8EZeYBqeqMD5AOFxjM5OMD160RrdVYa+fwotkcFQzFV2DVNUEysxK+?= =?us-ascii?Q?ANlu60GwVqGey92avdrMPPbnDhcCc2Bzmchf5slb5TzveMBZ9F0fzOgS8jjk?= =?us-ascii?Q?Qg=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 639d618e-b60e-4a3a-107c-08dab1e380f5 X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6059.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2022 15:06:30.8408 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mx7q5G1W3h9LMoIPHUJFVsMEhBfeay/pZu6whboHp5aK4staYAZbrVRVdJr9VrOKziMrsgz22RUmNTUVjAEYdQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB4894 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: Use GEN12_RPSTAT register for GT freq X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Oct 18, 2022 at 10:20:40PM -0700, Ashutosh Dixit wrote: > From: Don Hiatt > > On GEN12+ use GEN12_RPSTAT register to get actual resolved GT > freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if > GT is in RC6. > > v2: > - Fixed review comments(Ashutosh) > - Added function intel_rps_read_rpstat_fw to read RPSTAT without > forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko) > v3: > - Updated commit title and message for more clarity (Ashutosh) > - Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in > read_cagf (Ashutosh) > > Cc: Don Hiatt > Cc: Andi Shyti > Signed-off-by: Don Hiatt > Signed-off-by: Badal Nilawar > Signed-off-by: Ashutosh Dixit > Reviewed-by: Andi Shyti > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ > drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++++++---- > drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++ > drivers/gpu/drm/i915/i915_pmu.c | 3 +-- > 4 files changed, 33 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 36d95b79022c0..a7a0129d0e3fc 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1543,6 +1543,8 @@ > > #define GEN12_RPSTAT1 _MMIO(0x1381b4) > #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) > +#define GEN12_CAGF_SHIFT 11 we don't need to define the shift if we use the REG_FIELD_GET > +#define GEN12_CAGF_MASK REG_GENMASK(19, 11) ah, cool, this is already right and in place (ignore my comment about this in the other patch) > > #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) > #define GEN11_CSME (31) > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index fc23c562d9b2a..df21258976d86 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -2068,12 +2068,34 @@ void intel_rps_sanitize(struct intel_rps *rps) > rps_disable_interrupts(rps); > } > > +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + i915_reg_t rpstat; > + > + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; > + > + return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat); > +} > + > +u32 intel_rps_read_rpstat(struct intel_rps *rps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + i915_reg_t rpstat; > + > + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; > + > + return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat); > +} > + > u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > { > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 cagf; > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > + if (GRAPHICS_VER(i915) >= 12) > + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); > + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > cagf = (rpstat >> 8) & 0xff; > else if (GRAPHICS_VER(i915) >= 9) > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; > @@ -2094,7 +2116,9 @@ static u32 read_cagf(struct intel_rps *rps) > struct intel_uncore *uncore = rps_to_uncore(rps); > u32 freq; > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > + if (GRAPHICS_VER(i915) >= 12) { > + freq = intel_uncore_read(uncore, GEN12_RPSTAT1); > + } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > vlv_punit_get(i915); > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > vlv_punit_put(i915); > @@ -2260,7 +2284,7 @@ static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); > rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); > > - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1); > + rpstat = intel_rps_read_rpstat(rps); > rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; > rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; > rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; > @@ -2395,7 +2419,7 @@ static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > drm_printf(p, "PM MASK=0x%08x\n", pm_mask); > drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", > rps->pm_intrmsk_mbz); > - drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1)); > + drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps)); > drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps)); > drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", > intel_gpu_freq(rps, caps.min_freq)); > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h > index 110300dfd4383..9e1cad9ba0e9c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.h > +++ b/drivers/gpu/drm/i915/gt/intel_rps.h > @@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); > u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); > u32 intel_rps_read_punit_req(struct intel_rps *rps); > u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); > +u32 intel_rps_read_rpstat(struct intel_rps *rps); > +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps); > void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps); > void intel_rps_raise_unslice(struct intel_rps *rps); > void intel_rps_lower_unslice(struct intel_rps *rps); > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index 958b37123bf12..67140a87182f8 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -371,7 +371,6 @@ static void > frequency_sample(struct intel_gt *gt, unsigned int period_ns) > { > struct drm_i915_private *i915 = gt->i915; > - struct intel_uncore *uncore = gt->uncore; > struct i915_pmu *pmu = &i915->pmu; > struct intel_rps *rps = >->rps; > > @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) > * case we assume the system is running at the intended > * frequency. Fortunately, the read should rarely fail! > */ > - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1); > + val = intel_rps_read_rpstat_fw(rps); > if (val) > val = intel_rps_get_cagf(rps, val); > else > -- > 2.38.0 >