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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?4CW8QDlyAyNjcCOdCukKJ5OZmyiDguHsgBzzFyZeK8V2h0P+ITVS72WVykqo?= =?us-ascii?Q?MAEvbTv+gJWtUMbmncxtvAvxU9BQrFDB0DrgmLpaALfxE2UIwGX+DfPguskV?= =?us-ascii?Q?qs4PpJZCa95fJx4RXGJibW+n81iqq7WdvlTbLrjGj7FnPkHd3XW5cby73ZDs?= =?us-ascii?Q?19dTuazdvqmQziV4qAtCHskhL99oisbIkXSZPpyBGNDSdxkw00ektQqTVsi1?= =?us-ascii?Q?7KW33QlOgpNVMzfVAyPWAQYLHIKgOsBxX+15puxzrZOk4VkWd8xFR362tIZF?= =?us-ascii?Q?5S1fVkb5jIe0Ut7EgCKq1m4QNN+hDhobw7IxqrpUS8GqM7x5THqCO9m+I2Jx?= =?us-ascii?Q?qjSpwo0wCAByD8DVlY3y1Djh7KETqAtEz07koP2UGOsxpALFZXbee6KAsrim?= =?us-ascii?Q?vosh4WGhG2r4sN/3zWygoQM/EbyqgdUAf8zYL7lc3Z00TnOWWWfdlVS0Bw63?= =?us-ascii?Q?f+EaKA0LxVw0X61bbKP2feaA2TtDZNfQiZJtMVW5+yZZCtJu55fWO2RW5zyH?= =?us-ascii?Q?ue/R19ok233sDy8oBjm2vvnLfiTT+CIxx0uBe+lIaRMh3VMQB96KPsKlK6af?= =?us-ascii?Q?qANE25g/N2tPca1ptaGrFthMfjNBomBiy871dphSNQKNpf1rsH7GtCGBFbpX?= =?us-ascii?Q?Qgg2yF7VhrfWsLn7LdjMlmT+6hzJ34SBMzE3nLi2Y9r069Q1laPluVgF95gH?= =?us-ascii?Q?TuEmDtMjEhhjszURb/FV1Zqxjz6XI9sZ13GJbLclAkH8upJTnrumWXIDmmwB?= =?us-ascii?Q?U2eUAZAJ0BsnRDvBIk9kCkspJIizBoayNyZuwU8x1LT8I3MmLNmC7jDW4ufx?= =?us-ascii?Q?JcOrBnMBZbGQEEDpE+KqOSlMU7JOLmr//UDCe6flk1gHdWtK7R1LeZCQauec?= =?us-ascii?Q?63o/vVxa5FcRMbhyOujO7KDktPt0foG6MW6BXVlvwV9ZvQSCOGXOvHCc5UZ5?= =?us-ascii?Q?peaeC/jd3GPSZ7PEIv4wgdEQJc4hc9X52PjEz6pZ8alGssiM4QC0mqKZUN6I?= =?us-ascii?Q?k33IfiqaTJz/NbEEEvhHKRG14WjTVuMMZGi6dq3+E07CqhQap5/GL3E9It6f?= =?us-ascii?Q?Jg6w+s9YqPGn5H7ZQ+I2exwgt5cuEJRs6reboo6/RsA2/3HG2Fky5s38ljiD?= =?us-ascii?Q?lS/YQ1Nr3JOhI5DWhy+sQer9pS/HV/GnDmU/dCEQYz3E+yCqprCEqe6Qjo8G?= =?us-ascii?Q?n8uujspRKi+9bjHT6iz7PxMyRAUckAIRdj4KdQ4pkSBbWVyKoByrwebgrQUM?= =?us-ascii?Q?rObL5APCqzrxvkgJ1OCmt3j9a2noiDLYpfZnNjiDWAr7G/C+M18XnKmu0jA8?= =?us-ascii?Q?GtEHrQT60WVREnqTFvTdY1qFXQPwlbkyuozYw10ALCzB7aSDjVXwjSdEk9Ds?= =?us-ascii?Q?4wcw4DfI/UmbjbjlL3PX/DEEqz+aedX+Q+HMNy/bhWSpKu3sLSSiMEwEJMQN?= =?us-ascii?Q?TJMr+o8LxlSmmn7AzwDC0TFcGXLxYajznoZ+BTmxnGUUQkZoRH2IiJZPWP9z?= =?us-ascii?Q?T4+n2DTD/uT+iUDZq7uoTBOtYcb4YJEATa95IW/hgyr7/fWg8U1ljBjRsGBV?= =?us-ascii?Q?Pytod65ysTBtjwQPBq33IRgIWcdOB9bYt28iU8xKIj7l95+E3N0D0+vmbQGo?= =?us-ascii?Q?dA=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: d0a5b3ee-1a5a-44ef-b202-08dab37f0766 X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6059.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 16:12:19.4923 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: UWwY3f3QkxwEdZ75g9UZCcbd8Tzqhb3bKPCOa8Hg1Q82/4PaAOBhMOCqd3BpUlc+M0vr9kI4wpM8Ng1biQkuxg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR11MB5254 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH 2/5] drm/i915: Use GEN12_RPSTAT register for GT freq X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Oct 19, 2022 at 04:37:18PM -0700, Ashutosh Dixit wrote: > From: Don Hiatt > > On GEN12+ use GEN12_RPSTAT register to get actual resolved GT > freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if > GT is in RC6. > > v2: > - Fixed review comments(Ashutosh) > - Added function intel_rps_read_rpstat_fw to read RPSTAT without > forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko) > v3: > - Updated commit title and message for more clarity (Ashutosh) > - Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in > read_cagf (Ashutosh) > v4: Remove GEN12_CAGF_SHIFT and use REG_FIELD_GET (Rodrigo) > > Cc: Don Hiatt > Cc: Andi Shyti > Signed-off-by: Don Hiatt > Signed-off-by: Badal Nilawar > Signed-off-by: Ashutosh Dixit > Reviewed-by: Andi Shyti Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++++++---- > drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++ > drivers/gpu/drm/i915/i915_pmu.c | 3 +-- > 4 files changed, 32 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 35c039573294c..f8c4f758ac0b1 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1539,6 +1539,7 @@ > > #define GEN12_RPSTAT1 _MMIO(0x1381b4) > #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) > +#define GEN12_CAGF_MASK REG_GENMASK(19, 11) > > #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) > #define GEN11_CSME (31) > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index 5bd6671554a6e..da6b969f554b6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -2068,12 +2068,34 @@ void intel_rps_sanitize(struct intel_rps *rps) > rps_disable_interrupts(rps); > } > > +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + i915_reg_t rpstat; > + > + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; > + > + return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat); > +} > + > +u32 intel_rps_read_rpstat(struct intel_rps *rps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + i915_reg_t rpstat; > + > + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; > + > + return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat); > +} > + > u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > { > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 cagf; > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > + if (GRAPHICS_VER(i915) >= 12) > + cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); > + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > cagf = REG_FIELD_GET(RPE_MASK, rpstat); > else if (GRAPHICS_VER(i915) >= 9) > cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat); > @@ -2093,7 +2115,9 @@ static u32 read_cagf(struct intel_rps *rps) > struct intel_uncore *uncore = rps_to_uncore(rps); > u32 freq; > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > + if (GRAPHICS_VER(i915) >= 12) { > + freq = intel_uncore_read(uncore, GEN12_RPSTAT1); > + } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > vlv_punit_get(i915); > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > vlv_punit_put(i915); > @@ -2259,7 +2283,7 @@ static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); > rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); > > - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1); > + rpstat = intel_rps_read_rpstat(rps); > rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; > rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; > rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; > @@ -2394,7 +2418,7 @@ static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > drm_printf(p, "PM MASK=0x%08x\n", pm_mask); > drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", > rps->pm_intrmsk_mbz); > - drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1)); > + drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps)); > drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps)); > drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", > intel_gpu_freq(rps, caps.min_freq)); > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h > index 110300dfd4383..9e1cad9ba0e9c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.h > +++ b/drivers/gpu/drm/i915/gt/intel_rps.h > @@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); > u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); > u32 intel_rps_read_punit_req(struct intel_rps *rps); > u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); > +u32 intel_rps_read_rpstat(struct intel_rps *rps); > +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps); > void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps); > void intel_rps_raise_unslice(struct intel_rps *rps); > void intel_rps_lower_unslice(struct intel_rps *rps); > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index 958b37123bf12..67140a87182f8 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -371,7 +371,6 @@ static void > frequency_sample(struct intel_gt *gt, unsigned int period_ns) > { > struct drm_i915_private *i915 = gt->i915; > - struct intel_uncore *uncore = gt->uncore; > struct i915_pmu *pmu = &i915->pmu; > struct intel_rps *rps = >->rps; > > @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) > * case we assume the system is running at the intended > * frequency. Fortunately, the read should rarely fail! > */ > - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1); > + val = intel_rps_read_rpstat_fw(rps); > if (val) > val = intel_rps_get_cagf(rps, val); > else > -- > 2.38.0 >