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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?KPtH/XEr65Bnd0pJkTzS1jxUpTfxM4VWixiB5jSNtNG4/AppXWP5E4Atze3P?= =?us-ascii?Q?cDi+Htb0j9VlwN80bbhJiQqRvrjkq7dA6uIl+9nnNDEolno0bfFQQQePiEEC?= =?us-ascii?Q?hl09kLdaWZlqkqr7mXiqJMHEATlxJZe5DK8RJict6O5JCCLE5BiRdE5nWm5R?= =?us-ascii?Q?94hEyE/9U0s9RW5tDfDRXpxsYs3+wgaK6Jr/5X0q1kdy8Fr8nv6JK5XvJX2O?= =?us-ascii?Q?IU+nVJeNnUFz81NRVILGPQ42wTVSvuAQ6SQqUCLGZbzPLZXQtozNb24qqZWU?= =?us-ascii?Q?54TZCVThr0QUEq5yTugmajp4YmdJDGlhf3ZwV7CHLB05EPU3u0rZFANcHb+U?= =?us-ascii?Q?K/q9+BqviUQ6d8qqyJ8eI1aQtk7ZOPArPj7C9Qw8Z0zy3XUQ5V0FSj2KP5Fg?= =?us-ascii?Q?gp7vhDdKOdRhHRPTOf2fTinghrn4yUcB0o4cuYCo60sCgU0ok80MjW3KC2wV?= =?us-ascii?Q?IUUjEQnr9Dh8cnlJ4gye0Bhf48HJq5Dzdx80NdKswInvmkYXBzekzqWrj0Oo?= =?us-ascii?Q?GcPvMyAuh0Fof3DrgufPV3omJGJYiA8VgLAPVVDnQWpajgVuttekEbK3NtDB?= =?us-ascii?Q?txYgc2k1NKkwlY9iU2eMt8BlysgxLyS1hqxPVkev/H7Q71Z1BoXGEmHB2/ER?= =?us-ascii?Q?QWoOQilhYpxOyzSoS1cujuUVDiotX/oay3kInWmbo9tADvPzSi9TPAZruCkP?= =?us-ascii?Q?vsTZp3t39XaHGl1KKOd9zpRNX77Sv8bdV38detApY8/9CH4BPm3e1QCvpm71?= =?us-ascii?Q?ZRck+yB7p7/6t5tUrflz8D4tJbOUgIEutUKdF5BJn+DCTYgRPcbRNZ2zgQoT?= =?us-ascii?Q?hYVLPNSjCVWDjCHKgozSwcMfpv3KNP8AUOyqsZUa1JfqrsL6AmERhdeQf8rQ?= =?us-ascii?Q?uMVuA0qQTo47rr67bjv9kTaqDW59T4ar3TYUMpKJ3BdrTwqhSgg+rh39iJ0J?= =?us-ascii?Q?UQ3WlwXzBXP85kePGryQ+bQFS8GgLJCLXypz0RNHPOziRYhwoP7PKXqLWMxv?= =?us-ascii?Q?QIuUS2IAiPSs1ahKJtpB077oo0GosKB0vBCpUPOThRZt+iULA6otBf5ys4UK?= =?us-ascii?Q?Mw5EUbQDdSX/23rSeQGyY4iOVoEmJ9sM6XeWmffzETwG5z/hJz16RVLhuUT2?= =?us-ascii?Q?zEdusGhV7VHMmDo5liQ+slCYWhlF4BfRBDyJAFFOPZGgQmO9FYoBvIHOGu0l?= =?us-ascii?Q?/FTfKKXKPua2dvh0DtUq24SDOIhYxCs1jsPxYnF4oVafBPc4cYemSm774qmI?= =?us-ascii?Q?hvmOop47SUSRz0bs4NwC3RufkJJewOR8l8VJV/BJPo7X83TwAwg5+bd6ekPU?= =?us-ascii?Q?HQgpQkhpYChdJ42C3hPqIt8RqOZoSi/wOy4g+mCKolaxcAknqCAsz6KODKrg?= =?us-ascii?Q?YgO54auUCIlXf7dp73g+97xF5vyROCUxyBuKXcn4UCjq1D/xmZCVpUZkQlzJ?= =?us-ascii?Q?RPLm9oy1JnfdL1rx7FUyj3RJ76ltp20QoLv9qx10RTieoTESIShGXEShOvVG?= =?us-ascii?Q?GBhoWOnSTQxWyeaA7abB68DRUcuDOjsoMgW08O6mTuuqM47TcjtBCtL0Ygn/?= =?us-ascii?Q?Jeeit6SrG14zNLuCHtnZWpPIifH/hLQ5f4s1m+Dzd1GTGqm3g686qDIblF27?= =?us-ascii?Q?8Q=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: ce5530be-f35a-4ded-71ab-08dac0ee72c6 X-MS-Exchange-CrossTenant-AuthSource: MWHPR11MB1632.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2022 18:32:38.8266 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZSykp14HE/uw31cPdsdsxD/1erwmw03rRar5lkC3z+zcB87Hoh9EWUjaTHtLK92rSgUxyVJ1O24+I/x3QgWChEV7sB34CwhufToz+NmPm8g= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR11MB6905 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH v2 3/5] drm/i915/mtl: add GSC CS interrupt support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Nov 02, 2022 at 10:10:45AM -0700, Daniele Ceraolo Spurio wrote: > The GSC CS re-uses the same interrupt bits that the GSC used in older > platforms. This means that we can now have an engine interrupt coming > out of OTHER_CLASS, so we need to handle that appropriately. > > v2: clean up the if statement for the engine irq (Tvrtko) > > Signed-off-by: Daniele Ceraolo Spurio > Cc: Matt Roper > Cc: Tvrtko Ursulin > Reviewed-by: Matt Roper #v1 Reviewed-by: Matt Roper for v2 as well. > --- > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 75 ++++++++++++++------------ > 1 file changed, 40 insertions(+), 35 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c > index f26882fdc24c..b197f0e9794f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c > @@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, > instance, iir); > } > > -static void > -gen11_engine_irq_handler(struct intel_gt *gt, const u8 class, > - const u8 instance, const u16 iir) > +static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance) > { > - struct intel_engine_cs *engine; > - > - /* > - * Platforms with standalone media have their media engines in another > - * GT. > - */ > - if (MEDIA_VER(gt->i915) >= 13 && > - (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) { > - if (!gt->i915->media_gt) > - goto err; > + struct intel_gt *media_gt = gt->i915->media_gt; > > - gt = gt->i915->media_gt; > + /* we expect the non-media gt to be passed in */ > + GEM_BUG_ON(gt == media_gt); > + > + if (!media_gt) > + return gt; > + > + switch (class) { > + case VIDEO_DECODE_CLASS: > + case VIDEO_ENHANCEMENT_CLASS: > + return media_gt; > + case OTHER_CLASS: > + if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0)) > + return media_gt; > + fallthrough; > + default: > + return gt; > } > - > - if (instance <= MAX_ENGINE_INSTANCE) > - engine = gt->engine_class[class][instance]; > - else > - engine = NULL; > - > - if (likely(engine)) > - return intel_engine_cs_irq(engine, iir); > - > -err: > - WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n", > - class, instance); > } > > static void > @@ -122,8 +114,17 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity) > if (unlikely(!intr)) > return; > > - if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS) > - return gen11_engine_irq_handler(gt, class, instance, intr); > + /* > + * Platforms with standalone media have the media and GSC engines in > + * another GT. > + */ > + gt = pick_gt(gt, class, instance); > + > + if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) { > + struct intel_engine_cs *engine = gt->engine_class[class][instance]; > + if (engine) > + return intel_engine_cs_irq(engine, intr); > + } > > if (class == OTHER_CLASS) > return gen11_other_irq_handler(gt, instance, intr); > @@ -206,7 +207,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt) > intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); > if (CCS_MASK(gt)) > intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0); > - if (HAS_HECI_GSC(gt->i915)) > + if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0)) > intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0); > > /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ > @@ -233,7 +234,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt) > intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0); > if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) > intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0); > - if (HAS_HECI_GSC(gt->i915)) > + if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0)) > intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0); > > intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); > @@ -249,7 +250,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) > { > struct intel_uncore *uncore = gt->uncore; > u32 irqs = GT_RENDER_USER_INTERRUPT; > - const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1); > + u32 gsc_mask = 0; > u32 dmask; > u32 smask; > > @@ -261,6 +262,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) > dmask = irqs << 16 | irqs; > smask = irqs << 16; > > + if (HAS_ENGINE(gt, GSC0)) > + gsc_mask = irqs; > + else if (HAS_HECI_GSC(gt->i915)) > + gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1); > + > BUILD_BUG_ON(irqs & 0xffff0000); > > /* Enable RCS, BCS, VCS and VECS class interrupts. */ > @@ -268,9 +274,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) > intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask); > if (CCS_MASK(gt)) > intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask); > - if (HAS_HECI_GSC(gt->i915)) > - intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, > - gsc_mask); > + if (gsc_mask) > + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask); > > /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ > intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); > @@ -296,7 +301,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) > intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask); > if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) > intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask); > - if (HAS_HECI_GSC(gt->i915)) > + if (gsc_mask) > intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask); > > /* > -- > 2.37.3 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation