From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4076FC4332F for ; Wed, 23 Nov 2022 18:54:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B112210E214; Wed, 23 Nov 2022 18:54:32 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 69A5910E214; Wed, 23 Nov 2022 18:54:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669229668; x=1700765668; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=BezJs16gFnfHzepGfGCLKiT17WjzzvvgqoxItc7WdnQ=; b=Nr0f4iKDhLQ4XVDWHVH9a/tRmkaCfwPMkjRAdSVBW36ScHbjhER1i3gK eWLPvB51wo1AP3/qODoPkT3N0n3ifmy++1I4Gco57elSWBt1FRXu95Iaj fEzGtRHKP2JLSU0OWX0B+Xb1nRO9HQKAkCy8KsqvEkHry5q7k+2wyK4ks YwNc3b8EynRwQTVZyKXzbK5nYseR6qpox3Na28W5NPmd0xUt4fcjGhIM8 eMSePTdMuAG9GyegxPADTkItmKzm1Fh82laZBjGt4bue8JpWa9u1SDM9C 5mOAIKa4Z02UxHeEMUmtmydESjOA45zLFw/qACKipvoaHWb05mFzhmFEd Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="297499091" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="297499091" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 10:54:27 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="710694785" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="710694785" Received: from ekemppi-mobl.ger.corp.intel.com (HELO intel.com) ([10.249.32.127]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 10:54:24 -0800 Date: Wed, 23 Nov 2022 19:54:21 +0100 From: Andi Shyti To: Tvrtko Ursulin Message-ID: References: <20221122185737.96459-1-andi.shyti@linux.intel.com> <20221122185737.96459-3-andi.shyti@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Intel-gfx] [PATCH v2 2/4] drm/i915: Introduce guard pages to i915_vma X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas =?iso-8859-15?Q?Hellstr=F6m?= , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Chris Wilson , Matthew Auld Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi Tvrtko, [...] > > @@ -768,6 +768,9 @@ i915_vma_insert(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, > > GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT)); > > GEM_BUG_ON(!is_power_of_2(alignment)); > > + guard = vma->guard; /* retain guard across rebinds */ > > + guard = ALIGN(guard, alignment); > > Why does guard area needs the same alignment as the requested mapping? What about the fact on 32-bit builds guard is 32-bit and alignment u64? I guess this just to round up/down guard to something, not necessarily to that alignment. Shall I remove it? [...] > > @@ -777,6 +780,7 @@ i915_vma_insert(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, > > if (flags & PIN_ZONE_4G) > > end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE); > > GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE)); > > + GEM_BUG_ON(2 * guard > end); > > End is the size of relevant VA area at this point so what and why is this checking? I think because we want to make sure the padding is at least not bigger that the size. What is actually wrong with this. [...] > > @@ -855,6 +869,7 @@ i915_vma_insert(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, > > GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, color)); > > list_move_tail(&vma->vm_link, &vma->vm->bound_list); > > + vma->guard = guard; > > unsigned long into u32 - what guarantees no truncation? we are missing here this part above: guard = vma->guard; /* retain guard across rebinds */ if (flags & PIN_OFFSET_GUARD) { GEM_BUG_ON(overflows_type(flags & PIN_OFFSET_MASK, u32)); guard = max_t(u32, guard, flags & PIN_OFFSET_MASK); } that should make sure that we fit into 32 bits. [...] > > @@ -197,14 +197,15 @@ struct i915_vma { > > struct i915_fence_reg *fence; > > u64 size; > > - u64 display_alignment; > > struct i915_page_sizes page_sizes; > > /* mmap-offset associated with fencing for this vma */ > > struct i915_mmap_offset *mmo; > > + u32 guard; /* padding allocated around vma->pages within the node */ > > u32 fence_size; > > u32 fence_alignment; > > + u32 display_alignment; > > u64 -> u32 for display_alignment looks unrelated change. > > ./display/intel_fb_pin.c: vma->display_alignment = max_t(u64, vma->display_alignment, alignment); > ./gem/i915_gem_domain.c: vma->display_alignment = max_t(u64, vma->display_alignment, alignment); > > These two sites need to be changed not to use u64. > > Do this part in a separate patch? Right! will remove it. > > /** > > * Count of the number of times this vma has been opened by different > > Regards, Thanks, Andi > Tvrtko