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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?k9l2+agG/erBcR3E7ouMX7oyCBOdGAe6yKmgJRRzGI/ZijoJrQDkrJh8OnFp?= =?us-ascii?Q?2xEFoe0X8dgNI2VhlrwoRtqMh8u+4fzBPw7j0WuptEYcyrLc4khljESqGqJ7?= =?us-ascii?Q?3WOSR8yjv8EzLX8OJfeRziWi2vrL26Yhfexllyj+ANLyM0gWIlTaukTxv9TA?= =?us-ascii?Q?LgFFdBuUV5D844oCZd2tA9Y02/iT3U2RIscME2wP3jY8LKGei5RoR8lxYfTW?= =?us-ascii?Q?a/GEb4u4w/YN+y03nKkJoaRi/mfUVhPMGV/Ewm0J4pblehhO4B8xntSxDQqa?= =?us-ascii?Q?s/BeL/EG8OqveJyrQGfMkKrk4fQe7CAP888Mris1yDKHv9DnYdZVn6O2jKbJ?= =?us-ascii?Q?Owfjm3mHvTvB9Y+uCHqnoCSzJNX2dAASKAVr5C85QaeQlzZSx3nEqNmcjFG9?= =?us-ascii?Q?sZT+2zyqHtS+yDomNiFl8UbDEGRlohGZuRd5CWODDT6wJ0m9hq0iXuHxfClg?= =?us-ascii?Q?O0KZt+oo0AHe0Uh8zHJtCV3Rre6vGf5tk0vvt7Aw71RDM5Li5NS+mPXP0NDt?= =?us-ascii?Q?XaLk1Y03ahpkCtdRTtoANWFHI+342fZRzs8Ptdo8gJRiXceQAvhQQQdhFZ9z?= =?us-ascii?Q?klohIZ/+E9eMC10brCYASlgxxOe2fOG6Zh8iDExwGTTDM4YQGUGIHVXLDN52?= =?us-ascii?Q?RTYkg0qIBD27iT7T58cGGdG1sa7mlOL48aGgk53JieMTf3Q++BUdCySSk2V2?= =?us-ascii?Q?JCj7apCMIautKoHTSFxlH1+RyNVJsmfayQJfQDsT3vSPLbk9wFDhxp2sSOOo?= =?us-ascii?Q?7LSpoMMm9PexKsnhVTc3mCyv+SSZg8soDypNwMj2EcgDxjCvjcPI2qXGDbTx?= =?us-ascii?Q?tzfhnSB8dnhPWxNmCrFesll8X72rma1sT6iPv3xsnOa5t7vQTtxCjwWX26+3?= =?us-ascii?Q?KKrpbT+06NH7QMEPxBhvHSzgqD6sZr9ENjzh+IGpuf6Q6HB20hZfGOJ7gp26?= =?us-ascii?Q?HUBvwpLzbxQv7DBD2ca5Qn25JsvMmQuaI4HLFhjQtFaiHYICvQNvGS3I0hNM?= =?us-ascii?Q?4kixZeQiW3KbZX74gggzKHY0hQPr//b+rSDy/RfU5ybip+iUQHOJM1EFQOq5?= =?us-ascii?Q?6lnYBwkmJd6E8vPCMz9FQi/G6s1TO10WvkhsYrMk9ZTY0Ci5bdxpW1pSbkui?= =?us-ascii?Q?Idx5n6/T4JOH61WUenfZQWzrM7KvtCHkdUbf3rtzgLQXdSJ+gHOkKHE+5gnK?= =?us-ascii?Q?Y/A2dfbIPZ0Kvn0FdiAVv5yBYVjjkMNtqij0gEDo7d/UmGTyM35iRhno4Ua+?= =?us-ascii?Q?QxOAp8zzhpDh51SzEuQlgNJt3EMoHaOi1BluOPLaY+eON4pfRrdGSKOcqJ/K?= =?us-ascii?Q?wLVFxe5rcZX26cGAML4kVT8YqZi6k9O+BLIqOM+AKW4CSx64XYZHc++KdVDT?= =?us-ascii?Q?HXmo+yBho+dgBOPe7M36UW0lKKnx7mbiSwkvcM1VbK4KVACUg93aiI+j6bpB?= =?us-ascii?Q?D7ObWMHAzQz7sxwMgaJyJeFGGtcq99VH5+y9BuOovPHv8QfHCXlmJ1F+QPCO?= =?us-ascii?Q?qx+D8DOUOwjLWOhAgyBAJ0eBK+c7ytiL3kwzPjUiRqK1izPIbZdfcBP52uMX?= =?us-ascii?Q?LL7RoO3X5LdyLyEDpq9SlIekcafu1z6KCPxQVwJe?= X-MS-Exchange-CrossTenant-Network-Message-Id: cdd88e5a-a344-4611-7e29-08dac8b57d10 X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6059.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2022 16:05:04.6102 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iEJE9dtjbpNx7nysocrsJ52Pq0zCkkXuucFVKxAa2a8Wy9EY7TIwF+znv3gnj+L1MWZYO9ZiyPPNbJs/IdeeDg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR11MB5651 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH v4 3/6] drm/i915/pxp: Make intel_pxp_is_active implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Nov 16, 2022 at 04:30:15PM -0800, Alan Previn wrote: > Make intel_pxp_is_active a global check and implicitly find > the PXP-owning-GT. > > As per prior two patches, callers of this function shall now > pass in i915 since PXP is a global GPU feature. Make > intel_pxp_is_active implicitly find the right gt so it's transparent > for global view callers (like display or gem-exec). > > However we also need to expose the per-gt variation of this for internal > pxp files to use (like what intel_pxp_is_active was prior) so also expose > a new intel_gtpxp_is_active function for replacement. > > Signed-off-by: Alan Previn > --- > drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- > drivers/gpu/drm/i915/pxp/intel_pxp.c | 14 ++++++++++++-- > drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 ++- > drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 4 ++-- > drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 2 +- > 5 files changed, 18 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c > index c123f4847b19..165be45a3c13 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c > @@ -271,7 +271,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915, > */ > pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm); > > - if (!intel_pxp_is_active(&to_gt(i915)->pxp)) > + if (!intel_pxp_is_active(i915)) > ret = intel_pxp_start(&to_gt(i915)->pxp); > } > > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c > index 88105101af79..76a924587543 100644 > --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c > @@ -87,11 +87,21 @@ bool intel_pxp_is_enabled(struct drm_i915_private *i915) > return intel_pxp_is_enabled_on_gt(>->pxp); > } > > -bool intel_pxp_is_active(const struct intel_pxp *pxp) > +bool intel_pxp_is_active_on_gt(const struct intel_pxp *pxp) if we are asking about the gt we should pass gt > { > return pxp->arb_is_valid; > } > > +bool intel_pxp_is_active(struct drm_i915_private *i915) > +{ > + struct intel_gt *gt = i915_to_pxp_gt(i915); > + > + if (!gt) > + return false; > + > + return intel_pxp_is_active_on_gt(>->pxp); > +} > + > /* KCR register definitions */ > #define KCR_INIT _MMIO(0x320f0) > /* Setting KCR Init bit is required after system boot */ > @@ -287,7 +297,7 @@ int intel_pxp_key_check(struct intel_pxp *pxp, > struct drm_i915_gem_object *obj, > bool assign) > { > - if (!intel_pxp_is_active(pxp)) > + if (!intel_pxp_is_active_on_gt(pxp)) > return -ENODEV; > > if (!i915_gem_object_is_protected(obj)) > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h > index 3f71b1653f74..fe981eebf0ec 100644 > --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h > @@ -19,7 +19,8 @@ bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp); > > bool intel_pxp_is_enabled_on_gt(const struct intel_pxp *pxp); > bool intel_pxp_is_enabled(struct drm_i915_private *i915); > -bool intel_pxp_is_active(const struct intel_pxp *pxp); > +bool intel_pxp_is_active_on_gt(const struct intel_pxp *pxp); > +bool intel_pxp_is_active(struct drm_i915_private *i915); > > void intel_pxp_init(struct intel_pxp *pxp); > void intel_pxp_fini(struct intel_pxp *pxp); > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c > index 4d257055434b..52a808fd4704 100644 > --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c > @@ -25,7 +25,7 @@ static int pxp_info_show(struct seq_file *m, void *data) > return 0; > } > > - drm_printf(&p, "active: %s\n", str_yes_no(intel_pxp_is_active(pxp))); > + drm_printf(&p, "active: %s\n", str_yes_no(intel_pxp_is_active_on_gt(pxp))); > drm_printf(&p, "instance counter: %u\n", pxp->key_instance); > > return 0; > @@ -43,7 +43,7 @@ static int pxp_terminate_set(void *data, u64 val) > struct intel_pxp *pxp = data; > struct intel_gt *gt = pxp_to_gt(pxp); > > - if (!intel_pxp_is_active(pxp)) > + if (!intel_pxp_is_active_on_gt(pxp)) > return -ENODEV; > > /* simulate a termination interrupt */ > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c > index d3c697bf9aab..c25c1979cccc 100644 > --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c > @@ -86,7 +86,7 @@ void intel_pxp_irq_disable(struct intel_pxp *pxp) > * called in a path were the driver consider the session as valid and > * doesn't call a termination on restart. > */ > - GEM_WARN_ON(intel_pxp_is_active(pxp)); > + GEM_WARN_ON(intel_pxp_is_active_on_gt(pxp)); > > spin_lock_irq(gt->irq_lock); > > -- > 2.34.1 >