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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?iso-8859-1?Q?Wn5J2PiK/Df8J2Fabfjh8EwGjluseQkBGTljVNigUaEdeg4+4Qg0m40B53?= =?iso-8859-1?Q?oHDsE11Vs/fa0fBeP4+hm50aYrbukGMZmt9zuM2ElaJhd2ZgFn8qAHSX4p?= =?iso-8859-1?Q?bn8+y/tMwXwMewcvnf3py+bl9WVfj1uqZAP+i4cssWUZN3z0Z5XVYBk86o?= =?iso-8859-1?Q?3npQ8WmkjFw1ou38hwwBj1Yuj6lA08WbflBG8wnueM9BcWTD6ClKPTLbyw?= =?iso-8859-1?Q?6eIT6f1kXlJuBbwGihJMmvP7B2mm3qWOh7wu0OceM1WlZSA2XzsCyuNcL6?= =?iso-8859-1?Q?jCCJPOy0i29noQoz9YR7Kd7UrZ1jrvgDFJY9/zjMYq4+6TK5bWxAIvI5AH?= =?iso-8859-1?Q?tHfp2aga2Iw4Lf3mLONDgI3J9hof/LmScobDldCBGctLdiHHvwNJKl+BSx?= =?iso-8859-1?Q?mjKsJb64Q+HuVeCeJkSspnTLfpk7Btj33G+eoo6DQ797KZf7TtL2CWtgge?= =?iso-8859-1?Q?vYFZVjHYZ9WGVSyce2ZL36HrEdiTTW7IVtKsr6lrGSZ82+NyrMZMsHdaju?= =?iso-8859-1?Q?jMF2JvvMMGI1/ObixEE9b2x4Bw8pYhbZrXFXHxWwFyklI7p5dRI+mO2TOa?= =?iso-8859-1?Q?yBVRtFbP6PxLdFlEzWAAtPa+s8oT3bVCgAgwLm+Rs0xa9ZmjkbC1W9XOUw?= =?iso-8859-1?Q?EaGDGpuAywiUeuhe5A/GJck08sEJ6pVpfI/e5RKfelIQee/HlyBWBtUpBr?= =?iso-8859-1?Q?InErTUv42/859KG+fafWal4LVH0CZ+zHK7mFqwMPeLan+9J/RBBZRYxRTz?= =?iso-8859-1?Q?rq+3EzpEu2nogoIWEyjmts5hlu0HiacJJVR0ThN2lYZafxhw2dBc0NRv/U?= =?iso-8859-1?Q?6WTP90w/46OT5bTnZVMeMoT7xHCadqp6kdH7e29jVX/XjHai15mxwMobbi?= =?iso-8859-1?Q?lfErHfEdmRBnDnD7mKQvrnYPPj+aHQC9qdtzwM5t7O06PG46yvT3DL0CaJ?= =?iso-8859-1?Q?KUy4KofEdU6Qo7LE/4q9ydJf9DByZf/wKS3AdUWdAnwYDFzNukjQwW/4e0?= =?iso-8859-1?Q?O956MHWWkRheNrjGFsaHynTKWSp9Uoui38WG+iEHXbE2SjzvjQR/25hi6i?= =?iso-8859-1?Q?G8Extej+T1wfNIUDzsaF+5obOfnH6b86W3YTyWnSKsLFrSSYeDJc0N5wY/?= =?iso-8859-1?Q?q3N2gGdemuBSEdEq+cPnxaljqXbglu4jsS5fDPNMJwwx5lRQ1lSQksi+b9?= =?iso-8859-1?Q?gkhfhk5wrBIBqWZh2NrFcuuDNSnh6OKxxHm4VcYDQtG4B2Vpr+CQnlJCvd?= =?iso-8859-1?Q?ySmnBs4yDXQCSnvJ7RLHAIeKh1XlcRxnHtwmCao7l+zhHAJrdevb9f1xnF?= =?iso-8859-1?Q?HHaZaX43FPLM6PxtNN+nb6zmJc625znOnpuvgPmakoF9/LIHXBG2CSpDQb?= =?iso-8859-1?Q?961Xzz5IEq4+z4n+urh4C1b7oDE4Gre2qPik+Sdidch2syiafTDFpeg54S?= =?iso-8859-1?Q?vFfAVB9vwTsO4b9bqsP5rDi1qOtin+e9hBFQJCpkdSd+1wXXhjkVA+PFQK?= =?iso-8859-1?Q?mkpGayJtVkIwgRiMK27U6u4WVF/D1BK6GQkjcHBg693CJGo8CGE9UKSWBA?= =?iso-8859-1?Q?UP6gZ+NQlLet3RxIu/COWJko3iTAGWQWT8x96L0ULkRUfT68VzXRS5pRXs?= =?iso-8859-1?Q?OKgUVp9vNbi/TiTHcAYh8IdGLcmPy+luPw5k90i3lzo6LmJ53KDWzxgQ?= =?iso-8859-1?Q?=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 99679fb6-a000-4ea8-dd82-08dac8ff44d2 X-MS-Exchange-CrossTenant-AuthSource: MWHPR11MB1632.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2022 00:53:13.6824 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: P7XTetp+VJwLKD9B0NqUDpnH3i7FtWeKA2I8B9oOrB2XuueSkaDCT2KNEYzXvPeAi9/b+f3hDqrAyC+bAn0aYyWzcOa8grdZqU+7Z+YMb7E= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR11MB6507 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and squash when changing cdclk X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Balasubramani Vivekanandan Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Nov 17, 2022 at 03:00:01PM -0800, Anusha Srivatsa wrote: > From: Ville Syrjälä > > For MTL, changing cdclk from between certain frequencies has > both squash and crawl. Use the current cdclk config and > the new(desired) cdclk config to construtc a mid cdclk config. s/construtc/construct/ > Set the cdclk twice: > - Current cdclk -> mid cdclk > - mid cdclk -> desired cdclk > > Driver should not take some Pcode mailbox communication > in the cdclk path for platforms that are Display version 14 and later. > > v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk > change via modeset for platforms that support squash_crawl sequences(Ville) > > v3: Add checks for: > - scenario where only slow clock is used and > cdclk is actually 0 (bringing up display). > - PLLs are on before looking up the waveform. > - Squash and crawl capability checks.(Ville) > > v4: Rebase > - Move checks to be more consistent (Ville) > - Add comments (Bala) > v5: > - Further small changes. Move checks around. > - Make if-else better looking (Ville) > > v6: MTl should not follow PUnit mailbox communication as the rest of > gen11+ platforms.(Anusha) > > Cc: Clint Taylor > Cc: Balasubramani Vivekanandan > Signed-off-by: Anusha Srivatsa > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 181 +++++++++++++++++---- > 1 file changed, 150 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 25d01271dc09..1280a08b9c72 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -1727,37 +1727,79 @@ static bool cdclk_pll_is_unknown(unsigned int vco) > return vco == ~0; > } > > -static void bxt_set_cdclk(struct drm_i915_private *dev_priv, > - const struct intel_cdclk_config *cdclk_config, > - enum pipe pipe) > +static int cdclk_squash_divider(u16 waveform) > +{ > + return hweight16(waveform ?: 0xffff); > +} > + > +static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915, > + const struct intel_cdclk_config *old_cdclk_config, > + const struct intel_cdclk_config *new_cdclk_config, > + struct intel_cdclk_config *mid_cdclk_config) > +{ > + u16 old_waveform, new_waveform, mid_waveform; > + int size = 16; > + int div = 2; > + > + /* Return for vco ~0 (-1) and follow complete PLL disable and enable */ I don't think the mention of ~0 / -1 here is helpful; we added the helper function to hide those low-level implementation details. Just say something high-level about what you're actually trying to do like "If the PLL is in an unknown state, force a complete disable and re-enable." Aside from that (and the typo in the commit message), Reviewed-by: Matt Roper > + if (cdclk_pll_is_unknown(old_cdclk_config->vco)) > + return false; > + > + /* Return if both Squash and Crawl are not present */ > + if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) > + return false; > + > + old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); > + new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); > + > + /* Return if Squash only or Crawl only is the desired action */ > + if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || > + old_cdclk_config->vco == new_cdclk_config->vco || > + old_waveform == new_waveform) > + return false; > + > + *mid_cdclk_config = *new_cdclk_config; > + > + /* > + * Populate the mid_cdclk_config accordingly. > + * - If moving to a higher cdclk, the desired action is squashing. > + * The mid cdclk config should have the new (squash) waveform. > + * - If moving to a lower cdclk, the desired action is crawling. > + * The mid cdclk config should have the new vco. > + */ > + > + if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { > + mid_cdclk_config->vco = old_cdclk_config->vco; > + mid_waveform = new_waveform; > + } else { > + mid_cdclk_config->vco = new_cdclk_config->vco; > + mid_waveform = old_waveform; > + } > + > + mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * > + mid_cdclk_config->vco, size * div); > + > + /* make sure the mid clock came out sane */ > + > + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < > + min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); > + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > > + i915->display.cdclk.max_cdclk_freq); > + drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != > + mid_waveform); > + > + return true; > +} > + > +static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > + const struct intel_cdclk_config *cdclk_config, > + enum pipe pipe) > { > int cdclk = cdclk_config->cdclk; > int vco = cdclk_config->vco; > u32 val; > u16 waveform; > int clock; > - int ret; > - > - /* Inform power controller of upcoming frequency change. */ > - if (DISPLAY_VER(dev_priv) >= 11) > - ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, > - SKL_CDCLK_PREPARE_FOR_CHANGE, > - SKL_CDCLK_READY_FOR_CHANGE, > - SKL_CDCLK_READY_FOR_CHANGE, 3); > - else > - /* > - * BSpec requires us to wait up to 150usec, but that leads to > - * timeouts; the 2ms used here is based on experiment. > - */ > - ret = snb_pcode_write_timeout(&dev_priv->uncore, > - HSW_PCODE_DE_WRITE_FREQ_REQ, > - 0x80000000, 150, 2); > - if (ret) { > - drm_err(&dev_priv->drm, > - "Failed to inform PCU about cdclk change (err %d, freq %d)\n", > - ret, cdclk); > - return; > - } > > if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && > !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { > @@ -1793,11 +1835,62 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, > > if (pipe != INVALID_PIPE) > intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); > +} > + > +static void bxt_set_cdclk(struct drm_i915_private *dev_priv, > + const struct intel_cdclk_config *cdclk_config, > + enum pipe pipe) > +{ > + struct intel_cdclk_config mid_cdclk_config; > + int cdclk = cdclk_config->cdclk; > + int ret = 0; > + > + /* > + * Inform power controller of upcoming frequency change. > + * Display versions 14 and beyond do not follow the PUnit > + * mailbox communication, skip > + * this step. > + */ > + if (DISPLAY_VER(dev_priv) >= 14) > + /* NOOP */; > + else if (DISPLAY_VER(dev_priv) >= 11) > + ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, > + SKL_CDCLK_PREPARE_FOR_CHANGE, > + SKL_CDCLK_READY_FOR_CHANGE, > + SKL_CDCLK_READY_FOR_CHANGE, 3); > + else > + /* > + * BSpec requires us to wait up to 150usec, but that leads to > + * timeouts; the 2ms used here is based on experiment. > + */ > + ret = snb_pcode_write_timeout(&dev_priv->uncore, > + HSW_PCODE_DE_WRITE_FREQ_REQ, > + 0x80000000, 150, 2); > + > + if (ret) { > + drm_err(&dev_priv->drm, > + "Failed to inform PCU about cdclk change (err %d, freq %d)\n", > + ret, cdclk); > + return; > + } > > - if (DISPLAY_VER(dev_priv) >= 11) { > + if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, > + cdclk_config, &mid_cdclk_config)) { > + _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe); > + _bxt_set_cdclk(dev_priv, cdclk_config, pipe); > + } else { > + _bxt_set_cdclk(dev_priv, cdclk_config, pipe); > + } > + > + if (DISPLAY_VER(dev_priv) >= 14) > + /* > + * NOOP - No Pcode communication needed for > + * Display versions 14 and beyond > + */; > + else if (DISPLAY_VER(dev_priv) >= 11) > ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, > cdclk_config->voltage_level); > - } else { > + else > /* > * The timeout isn't specified, the 2ms used here is based on > * experiment. > @@ -1808,7 +1901,6 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, > HSW_PCODE_DE_WRITE_FREQ_REQ, > cdclk_config->voltage_level, > 150, 2); > - } > > if (ret) { > drm_err(&dev_priv->drm, > @@ -1965,6 +2057,28 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915) > skl_cdclk_uninit_hw(i915); > } > > +static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915, > + const struct intel_cdclk_config *a, > + const struct intel_cdclk_config *b) > +{ > + u16 old_waveform; > + u16 new_waveform; > + > + drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco)); > + > + if (a->vco == 0 || b->vco == 0) > + return false; > + > + if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) > + return false; > + > + old_waveform = cdclk_squash_waveform(i915, a->cdclk); > + new_waveform = cdclk_squash_waveform(i915, b->cdclk); > + > + return a->vco != b->vco && > + old_waveform != new_waveform; > +} > + > static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, > const struct intel_cdclk_config *a, > const struct intel_cdclk_config *b) > @@ -2771,9 +2885,14 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) > pipe = INVALID_PIPE; > } > > - if (intel_cdclk_can_squash(dev_priv, > - &old_cdclk_state->actual, > - &new_cdclk_state->actual)) { > + if (intel_cdclk_can_crawl_and_squash(dev_priv, > + &old_cdclk_state->actual, > + &new_cdclk_state->actual)) { > + drm_dbg_kms(&dev_priv->drm, > + "Can change cdclk via crawling and squashing\n"); > + } else if (intel_cdclk_can_squash(dev_priv, > + &old_cdclk_state->actual, > + &new_cdclk_state->actual)) { > drm_dbg_kms(&dev_priv->drm, > "Can change cdclk via squashing\n"); > } else if (intel_cdclk_can_crawl(dev_priv, > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation