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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?RHkdzZM4yTI3dZf2ZmtonaVWB+GebwYFAE689EXSnr7XA+MdI9C1yESjvDI9?= =?us-ascii?Q?zN0Vh2Y3ZDg1wrW0UP5WZLxKSPdHE7iJR2apUD1wDLNX9wnZKOzukNsdLdzn?= =?us-ascii?Q?TJETBbm82a4Rck/xKqHj2wO3BIWxA9P2xHOhojlVJTO3vudT4jNS6enR3cAQ?= =?us-ascii?Q?ieL6C/SLfKVJXzqUVAAMFQQag9XlvQqHcuwVS1/2Q22ypt0MnCViITGVkNsN?= =?us-ascii?Q?GDPz/0dYubkwRDxReEMGLc6tZhFsp8wnhwIwGK3eU9cSgGDCengILlQQslRg?= =?us-ascii?Q?knXLIrMFekzA/yuAHvCCITNCVdffTJ0u8URC+Mesnyk3KZHFsU8uO7rQpBvw?= =?us-ascii?Q?iht/G/6ZjUSVc86rBiIn1PMcmYD+n4+g8+G/ZFSwKCGhhDpALcc2fe1SsQgd?= =?us-ascii?Q?e2Rf+Di0UUj1szQ6XFYdbj2LMdsPI1grh6P4ukeX2Dzml0lA7xyhX9Avczto?= =?us-ascii?Q?f6gPXaROs7dK2T5Mw3qSPb7+Y41bLNn2YoRT4uh2A3egyCeYY7ImcK8ehntw?= =?us-ascii?Q?eG+QYWNWgePC4rqaPlxfCmeHgq6Z+siCr6ZPh/vbGIx8A0BwZhxrZBk1QSrb?= =?us-ascii?Q?ANGVyhvyXLlPO6tiITn8Hv7UopyQtj9DmVptawmUIuZas7el3tS1FHRiL0lD?= =?us-ascii?Q?55fNvVUrUOOq11fX65N/JJ4a6V5caIsOKFoAjOYN7TbgOP7ZtxGTTJaUXTSP?= =?us-ascii?Q?Cuf5YVgDMzEY0nS9e/iZS1W+1EK0MSGmtmolMApwqENoi8maFt5qnZbfN+vR?= =?us-ascii?Q?ZJyFYygdMbFc/0LQMbuNBG3L/LzJU0XwLINlvySpzEy254LtpY6vfeN8QK5D?= =?us-ascii?Q?u/4qNgQl3BcN7ahI6qN7bgre3yjsPGnDKXwCRUTvuUQX7YnLiPaWFectYVGS?= =?us-ascii?Q?SQjFNu7aAruP0IONlSQN1/MuHReZlLOi2Bii04BYopbaBPRL7U39hJMGX9ea?= =?us-ascii?Q?rOtN8EAtCNPC6LNRqn/E+iAiUXuWTdgMq3o33mjv16GRYBV4KVag13mmaQXH?= =?us-ascii?Q?SnC91kWUqWrbszFz4+BdVk5+b9vFZsdwYcWVSilozF+AxJeiJ1Ps7zFS7AvA?= =?us-ascii?Q?NthteCFDrM2mVjhEqHsSy/XvvMajRfM10yci/JGTbqcV+q2gsMRXzdsSVXs/?= =?us-ascii?Q?W00ZeZcP27OmTxnQotRbEe4zT1gJSnr3/vDXuw/IMRUT0HDP69kOQ4yX3rFP?= =?us-ascii?Q?X9/09cTlf8tfa8GonyM3RgKRYRFd5cTQHDofxoDQbyYemi7cFm/MbCqBOwO9?= =?us-ascii?Q?Azj7URsTlK4hylOuz27/6we0bI73tIxq7/ZJx+P8zU51SjnKQH9QZCmnMOKf?= =?us-ascii?Q?Y8fl3NttOcVi2Ncjh9ArBNwHcJQZ+qMnUApV8RyuV2pc1mlnEKwbYwcPw05W?= =?us-ascii?Q?fPoD3Irih2tnmn7AUdfdIeuC7o3hJTrYqxzDdz83wcNgcyZq/3qc0X5X/zQe?= =?us-ascii?Q?Er2Hdg5T0+gKcDklWwGtgNZmHurFuwdJvC1C0zxBFDckzVnYu+BT1t+ch25c?= =?us-ascii?Q?UvUZ+XXrAqQ1wBLQpVshgx2XIuTKjoyRSQnl5GNCYlM7lezzilTv5UofGoW9?= =?us-ascii?Q?RAW+JYMj4ZsjCi0+R6ZNdcXz4c/Xzk6Z6aBc26Iy9Ja9EcbDVM+qSzwA7sWx?= =?us-ascii?Q?9g=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 93dc3743-b3d6-43ec-505e-08dadec5d0f9 X-MS-Exchange-CrossTenant-AuthSource: MWHPR11MB1632.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 17:57:22.3988 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Pt7hYnr3/Pir5i5labFcDLOHg6/e0+Vf57dzTu3g9F/kfIPMCiuDKewe4As7bP+wSjU12omVdrhQhp5y3IqGOgTZcubyx5yL6rYVM13sRKk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB5087 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH] drm/i915: Skip Bit12 fw domain reset for gen12+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "intel-gfx@lists.freedesktop.org" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Dec 15, 2022 at 05:38:22PM +0000, Tvrtko Ursulin wrote: > > On 25/08/2022 18:49, Sripada, Radhakrishna wrote: > > Hi G.G, > > > > > -----Original Message----- > > > From: Mun, Gwan-gyeong > > > Sent: Tuesday, August 23, 2022 11:14 PM > > > To: Roper, Matthew D ; Sripada, Radhakrishna > > > > > > Cc: intel-gfx@lists.freedesktop.org > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Skip Bit12 fw domain reset for gen12+ > > > > > > > > > > > > On 8/18/22 3:00 PM, Matt Roper wrote: > > > > On Wed, Aug 17, 2022 at 03:43:04PM -0700, Radhakrishna Sripada wrote: > > > > > Bit12 of the Forcewake request register should not be cleared post > > > > > gen12. Do not touch this bit while clearing during fw domain reset. > > > > > > > > > > Bspec: 52542 > > > > > > > > > > Signed-off-by: Sushma Venkatesh Reddy > > > > > > > > Signed-off-by: Radhakrishna Sripada > > > > > --- > > > > > drivers/gpu/drm/i915/intel_uncore.c | 5 ++++- > > > > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c > > > b/drivers/gpu/drm/i915/intel_uncore.c > > > > > index a852c471d1b3..c85e2b686c95 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > > > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > > > > @@ -113,7 +113,10 @@ fw_domain_reset(const struct > > > intel_uncore_forcewake_domain *d) > > > > > * off in ICL+), so no waiting for acks > > > > > */ > > > > > /* WaRsClearFWBitsAtReset:bdw,skl */ > > > > > > > > While we're at it, let's remove the "bdw,skl" from this comment since > > > > it's misleading and doesn't match the code. We do still apply this > > > > workaround on other pre-gen12 platforms than just those two. > > > > > > > > Aside from the comment tweak, > > > > > > > > Reviewed-by: Matt Roper > > > > > > > > > - fw_clear(d, 0xffff); > > > > > + if (GRAPHICS_VER(d->uncore->i915) >= 12) > > > Hi Radhakrishna Sripada, > > > > > > In bspec 52542, there is an explanation that BIT12 should not be set for > > > address 0xA188 corresponding to FORCEWAKE_MT/FORCEWAKE_GT_GEN9, but > > > in > > > bspec 52466, there is no explanation that BIT12 should not be set for > > > address 0xA278, address of FORCEWAKE_RENDER_GEN9. > > > > > > I ask if fw_domain_reset() should perform fw_clear() by comparing not > > > only GRAPHICS_VER() >= 12 but also checking of FW_DOMAIN_ID_RENDER and > > > FW_DOMAIN_ID_GT values. > > Based on the note in 52542, all other WA notes are overridden by the comment. So unless stated > > otherwise, it should apply to this register as well. > > > > Created a bspec issue to request for additional clarification just to be safe. Will send an additional > > patch if the comment contradicts our understanding. > > How important was this patch - should it be sent to stable? It shouldn't be needed for stable; clearing the bit isn't necessary from gen12 onward, but as far as we know it doesn't cause any problems either (except maybe on MTL, which is still under force_probe and not supported on stable kernels). So according to stable-kernel-rules.rst, this patch would not qualify. Matt > > Regards, > > Tvrtko -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation