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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?PHj62xBQ1/7f4EpfbSL86iYoitvS+nrUvaxo6edL0vxuBWHL39Evy3d5TyJr?= =?us-ascii?Q?vhvPEoptfcFIgfsx+LT6C/6GN1YX3hmI3laaZgLDQN0/whAYT0/MFMF99Qm6?= =?us-ascii?Q?vyNStfgjx0uZkS6CfYZ2U1+NLOLw3Y/f1cymsZ+0NTTfIO6NzW5ZYpH9F+MJ?= =?us-ascii?Q?fST7Zn+5ZvaNH34KOKkoZZHwZv17YYxpb4eZJIM+7xIbRgUXs5wz81P0g1OS?= =?us-ascii?Q?MDVTKnioV5Jpqlb77GGn4r19dKLwUiRwMsZpeVPCALnWw63rj3O42W/ubZeF?= =?us-ascii?Q?tFYcbB7ZzM2lrN6MKgU8+2mzCCFIDc63kXb+JaKFyDLQd1O8g6Eb77YRLzHe?= =?us-ascii?Q?b9sRljjt7GQmR8X55LgGdfRfKwq/ZzbviKDcK4ssGVcqvBpw1BycWOVYVShw?= =?us-ascii?Q?upahJVbTimRqn7nWPXWDmPrg2kbMY1YvyYMtC/YpsFSnRv5+dcJU/oK9aW/Y?= =?us-ascii?Q?LXxAe60ZLO6pNZDsJJmoCSMDFC44lXBSkI1XZQBsov/q5q2DdoxH6IcvypjU?= =?us-ascii?Q?4UYwsgeky1Dka510spL1EI+zBuTsProyqLJIEquBq6eEoSST37oeEN2SyEtL?= =?us-ascii?Q?vDBEcfliJSeIhlri4OyttimCACuJ++SFnKSAFPl4qTRFFJ1u99bt8IkQphP9?= =?us-ascii?Q?5a8yQL5zqVB25fHhiGrFwR/fD3QZJjLstQBa1TGfbfI5KjIwg138WNhKWGr5?= =?us-ascii?Q?vKOJUENqfkvlISHg/JDS7ag06afnouGu+vWi+uMRyNnUaqEzOqjG9OzZKR0a?= =?us-ascii?Q?MeLFVhqxbm9PaS90aghD6quT7z0NSt9jArxysE06rRM02m3QWrYU3o/heDPf?= =?us-ascii?Q?gG9CxTnVD9LzsF4TmQGKr2OgqqHEjQK8SWio3J5qzyCgumMyNPgRCmgRqg/B?= =?us-ascii?Q?HhdKiK9/hRyUjjFdMTlCfVq5sTl4nuYxt1cZtue4qp3Vg5kiuMJyI7WqjV8i?= =?us-ascii?Q?ub6A6XGWNqdo06TDLtiTAXrrY86FX8yg1ernjqm9Ju0/Dqc8QWnD8PeGxahk?= =?us-ascii?Q?39xhRkIAlRzDDO8kSOQj7RE0sRmgLHZMXAaBddF2hvqwQ14U2l89pISILw5R?= =?us-ascii?Q?VUGdUptPWWpQOaYySYobvdVfWQNADOLoJPaHPSqv/VGlmM8TTbmbbArxE48d?= =?us-ascii?Q?3Zd41BY+1fYqcxd+IfqzQwMQSSMY9tudZdSLJSmjkTVxSnZcLX24brJowzhk?= =?us-ascii?Q?gKt+yoPLtJ4/TEu93rc7DBGoicbtWEyGSncZFW7dQ85HeY2n0ctxXqpprbC0?= =?us-ascii?Q?/gUJp0BPoPNiNNzU6s30NaZhQJSTAIiuGIqQioP1FArBBKIDZlBJ/gUE/TbK?= =?us-ascii?Q?cP01wd4/KjBZjJynOOC5osOrHxfd2LfPrFczUzuemvKMqgBVSuHMBmL3QQ0P?= =?us-ascii?Q?XRr1dUDmLalxm1l//hrlpkUFbOWUVUatw6L+iidf1ZQIdMfPOWWtJLJBt0Ij?= =?us-ascii?Q?vEZQnfeO0mauVvjcw0CCPpDQLuMPb/iWvML4+wY2jRbb21uWml2hRyPd1mlF?= =?us-ascii?Q?uVc3kbhJ59bTbHP/b/RwS4+B635TfHur0d81OIKOYqbD+RI63aug8T2clxSm?= =?us-ascii?Q?tx8MThljCfhMNZ6tBFNsnhI/g7UV8sY1CFjn0a1AA/bqDE1tDvh9L/LzVCjJ?= =?us-ascii?Q?MA=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 98b624cc-e781-4b0e-c6a6-08daeffaa15e X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6059.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2023 15:28:15.7065 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: eNKTv1AK5LVtVOeIeUhKNFlZ+3ZpDxAZpgwX+oMvfevgJO+jeQe8feGLapvMYZKrd/ciWopihEJhNZk+4UomBg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR11MB7455 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH v2 5/9] drm/i915/display/pch: use intel_de_rmw if possible X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Jan 05, 2023 at 02:10:42PM +0100, Andrzej Hajda wrote: > The helper makes the code more compact and readable. > > Signed-off-by: Andrzej Hajda Reviewed-by: Rodrigo Vivi > --- > .../gpu/drm/i915/display/intel_pch_display.c | 41 +++++-------------- > .../gpu/drm/i915/display/intel_pch_refclk.c | 10 +---- > 2 files changed, 13 insertions(+), 38 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c > index cecc0d007cf39c..4b5e069a1b9051 100644 > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c > @@ -307,7 +307,6 @@ static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum pipe pipe = crtc->pipe; > i915_reg_t reg; > - u32 val; > > /* FDI relies on the transcoder */ > assert_fdi_tx_disabled(dev_priv, pipe); > @@ -317,21 +316,16 @@ static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) > assert_pch_ports_disabled(dev_priv, pipe); > > reg = PCH_TRANSCONF(pipe); > - val = intel_de_read(dev_priv, reg); > - val &= ~TRANS_ENABLE; > - intel_de_write(dev_priv, reg, val); > + intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0); > /* wait for PCH transcoder off, transcoder state */ > if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) > drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", > pipe_name(pipe)); > > - if (HAS_PCH_CPT(dev_priv)) { > + if (HAS_PCH_CPT(dev_priv)) > /* Workaround: Clear the timing override chicken bit again. */ > - reg = TRANS_CHICKEN2(pipe); > - val = intel_de_read(dev_priv, reg); > - val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; > - intel_de_write(dev_priv, reg, val); > - } > + intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe), > + TRANS_CHICKEN2_TIMING_OVERRIDE, 0); > } > > void ilk_pch_pre_enable(struct intel_atomic_state *state, > @@ -456,21 +450,14 @@ void ilk_pch_post_disable(struct intel_atomic_state *state, > ilk_disable_pch_transcoder(crtc); > > if (HAS_PCH_CPT(dev_priv)) { > - i915_reg_t reg; > - u32 temp; > - > /* disable TRANS_DP_CTL */ > - reg = TRANS_DP_CTL(pipe); > - temp = intel_de_read(dev_priv, reg); > - temp &= ~(TRANS_DP_OUTPUT_ENABLE | > - TRANS_DP_PORT_SEL_MASK); > - temp |= TRANS_DP_PORT_SEL_NONE; > - intel_de_write(dev_priv, reg, temp); > + intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe), > + TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK, > + TRANS_DP_PORT_SEL_NONE); > > /* disable DPLL_SEL */ > - temp = intel_de_read(dev_priv, PCH_DPLL_SEL); > - temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); > - intel_de_write(dev_priv, PCH_DPLL_SEL, temp); > + intel_de_rmw(dev_priv, PCH_DPLL_SEL, > + TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0); > } > > ilk_fdi_pll_disable(crtc); > @@ -580,20 +567,14 @@ static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) > > static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) > { > - u32 val; > - > - val = intel_de_read(dev_priv, LPT_TRANSCONF); > - val &= ~TRANS_ENABLE; > - intel_de_write(dev_priv, LPT_TRANSCONF, val); > + intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0); > /* wait for PCH transcoder off, transcoder state */ > if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, > TRANS_STATE_ENABLE, 50)) > drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); > > /* Workaround: clear timing override bit. */ > - val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); > - val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; > - intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); > + intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); > } > > void lpt_pch_enable(struct intel_atomic_state *state, > diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c > index 08a94365b7d13b..6780c8fd9a1d31 100644 > --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c > +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c > @@ -12,19 +12,13 @@ > > static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv) > { > - u32 tmp; > - > - tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); > - tmp |= FDI_MPHY_IOSFSB_RESET_CTL; > - intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp); > + intel_de_rmw(dev_priv, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL); > > if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) & > FDI_MPHY_IOSFSB_RESET_STATUS, 100)) > drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n"); > > - tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); > - tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; > - intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp); > + intel_de_rmw(dev_priv, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0); > > if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) & > FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) > -- > 2.34.1 >