From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22750C433DB for ; Thu, 25 Mar 2021 09:56:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B287F61A23 for ; Thu, 25 Mar 2021 09:56:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B287F61A23 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2F4CA6ED01; Thu, 25 Mar 2021 09:56:20 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8A9466ED03 for ; Thu, 25 Mar 2021 09:56:18 +0000 (UTC) IronPort-SDR: DXpklNr/LkFVHjrIfdXwNnkm//ErxWNnptx08T8ZJrngli5BrL0oGCxjuQxl7pgK1QO3QkZNVY rXAfJv0uRSkw== X-IronPort-AV: E=McAfee;i="6000,8403,9933"; a="188597426" X-IronPort-AV: E=Sophos;i="5.81,277,1610438400"; d="scan'208";a="188597426" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2021 02:56:18 -0700 IronPort-SDR: 7uplAYxIZahmou7VigKZbT2998YQrKwZaJ9VP+HC69vC+6BxSI/YJNp6WxrME2ZiMRobHb8Wtw 3WFkVLJMenDQ== X-IronPort-AV: E=Sophos;i="5.81,277,1610438400"; d="scan'208";a="415922451" Received: from ssettalu-mobl1.amr.corp.intel.com (HELO intel.com) ([10.209.123.151]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2021 02:56:17 -0700 Date: Thu, 25 Mar 2021 05:56:15 -0400 From: Rodrigo Vivi To: Anshuman Gupta Message-ID: References: <20210325093213.20794-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210325093213.20794-1-anshuman.gupta@intel.com> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Tweaked Wa_14010685332 for all PCHs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david.e.box@intel.com, intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Mar 25, 2021 at 03:02:13PM +0530, Anshuman Gupta wrote: > dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform > despite Wa_14010685332 original sequence thus blocks entry to deeper s0ix state. > > The Tweaked Wa_14010685332 sequence fixes this issue, therefore use tweaked > Wa_14010685332 sequence for every PCH since PCH_CNP. > > Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platforms") > Cc: Matt Roper > Cc: Rodrigo Vivi > Signed-off-by: Anshuman Gupta > --- > .../drm/i915/display/intel_display_power.c | 18 +++++++++------- > drivers/gpu/drm/i915/i915_irq.c | 21 ------------------- > 2 files changed, 10 insertions(+), 29 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 7e0eaa872350..4e970be36487 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -5910,13 +5910,14 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915) > { > if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) { > bxt_enable_dc9(i915); > - /* Tweaked Wa_14010685332:icp,jsp,mcc */ > - if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC) > - intel_de_rmw(i915, SOUTH_CHICKEN1, > - SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); > } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { > hsw_enable_pc8(i915); > } > + > + /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,rkl,adp */ why are you adding "rkl"? I don't like mixing gpu with pch names... > + if (INTEL_PCH_TYPE(i915) == PCH_CNP || > + (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) < PCH_DG1)) why can't we simply use if (INTEL_PCH_TYPE(i915) >= PCH_CNP) ? > + intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); > } > > void intel_display_power_resume_early(struct drm_i915_private *i915) > @@ -5924,13 +5925,14 @@ void intel_display_power_resume_early(struct drm_i915_private *i915) > if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) { > gen9_sanitize_dc_state(i915); > bxt_disable_dc9(i915); > - /* Tweaked Wa_14010685332:icp,jsp,mcc */ > - if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC) > - intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); > - > } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { > hsw_disable_pc8(i915); > } > + > + /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,rkl,adp */ > + if (INTEL_PCH_TYPE(i915) == PCH_CNP || > + (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) < PCH_DG1)) > + intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); > } > > void intel_display_power_suspend(struct drm_i915_private *i915) > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 44aed4cbf894..8abcd35df926 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -3040,24 +3040,6 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv) > spin_unlock_irq(&dev_priv->irq_lock); > } > > -static void cnp_display_clock_wa(struct drm_i915_private *dev_priv) > -{ > - struct intel_uncore *uncore = &dev_priv->uncore; > - > - /* > - * Wa_14010685332:cnp/cmp,tgp,adp > - * TODO: Clarify which platforms this applies to > - * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as > - * on earlier platforms and whether the workaround is also needed for runtime suspend/resume > - */ > - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP || > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) { > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, > - SBCLK_RUN_REFCLK_DIS); > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); > - } > -} > - > static void gen8_irq_reset(struct drm_i915_private *dev_priv) > { > struct intel_uncore *uncore = &dev_priv->uncore; > @@ -3082,7 +3064,6 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv) > if (HAS_PCH_SPLIT(dev_priv)) > ibx_irq_reset(dev_priv); > > - cnp_display_clock_wa(dev_priv); > } > > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) > @@ -3123,8 +3104,6 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) > GEN3_IRQ_RESET(uncore, SDE); > - > - cnp_display_clock_wa(dev_priv); > } > > static void gen11_irq_reset(struct drm_i915_private *dev_priv) > -- > 2.26.2 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx