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Wed, 09 Jun 2021 07:54:11 -0700 (PDT) Date: Wed, 9 Jun 2021 16:54:10 +0200 From: Daniel Vetter To: Thomas =?iso-8859-1?Q?Hellstr=F6m?= Message-ID: References: <20210609063436.284332-1-thomas.hellstrom@linux.intel.com> <9f38fc28-15fb-2736-ba01-503821fdbe54@linux.intel.com> <4d570a5b-0ea7-71ab-5082-e67f0cd668a7@intel.com> <1cd6b04d-8928-14b3-a63d-c9ac2e81fcca@linux.intel.com> <99ff0d9f-9bd4-c27d-45a5-a66d2ad9064f@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <99ff0d9f-9bd4-c27d-45a5-a66d2ad9064f@linux.intel.com> X-Operating-System: Linux phenom 5.10.32scarlett+ Subject: Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Matthew Auld Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Jun 09, 2021 at 04:35:57PM +0200, Thomas Hellstr=F6m wrote: > = > On 6/9/21 3:08 PM, Thomas Hellstr=F6m wrote: > > = > > On 6/9/21 2:20 PM, Matthew Auld wrote: > > > On 09/06/2021 13:16, Thomas Hellstr=F6m wrote: > > > > = > > > > On 6/9/21 1:48 PM, Daniel Vetter wrote: > > > > > On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellstr=F6m wrot= e: > > > > > > A couple of patches from Chris which implement pipelined > > > > > > migration and > > > > > > clears by atomically writing the PTEs in place before performin= g the > > > > > > actual blit. > > > > > > = > > > > > > Some ww utilities mainly for the accompanying selftests > > > > > > added by Thomas, > > > > > > as well as modified the above patches for ww locking- > > > > > > and lmem support. > > > > > > = > > > > > > The actual hook up to the i915 ttm backend is being worked on a= nd not > > > > > > included yet, so this is considered to be an early > > > > > > review opportunity. > > > > > > = > > > > > > v2: > > > > > > - A couple of minor style fixes pointed out by Matthew Auld > > > > > > - Export and use intel_engine_destroy_pinned_context() to addre= ss a > > > > > > ls=A0=A0 CI warning / failure. > > > > > Just to check my understanding of the plan: These are the new win= dowed > > > > > clear/blt functions which we plan to use everywhere, because > > > > > less nasty > > > > > locking implications? And the clear/blt we currently have in > > > > > upstream will > > > > > be replaced? > > > > = > > > > Yes. These are for LMEM clearing and migration. It looks to me > > > > like the other ones we have in upstream are actually unused > > > > except for selftests. We're actually using CPU clearing for now. > > > > = > > > > > = > > > > > If so would be nice if this patch set includes that > > > > > replacement work (I > > > > > think right now all we have is the clear for lmem), > > > > > including updating of > > > > > selftests and stuff like that. Just to avoid having two ways to d= o the > > > > > same thing in the driver. > > > > = > > > > OK, I'll have a look at stripping the existing code. If we need > > > > it moving forward, we can always re-add. > > > = > > > Some low hanging fruit would be all the client_blt stuff which can > > > for sure be deleted now. > > = > > What has the client_blt stuff been used for? > > = > > In any case, I need 25 commits for commit access to be granted. > > = > > /Thomas > > = > > = > Series on trybot now. It's the dg1 live memory_region selftest that chang= es > sligthly to use the new migration fill blt. Thanks a lot for taking care of this! -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx