From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55BCFC433EF for ; Tue, 7 Sep 2021 17:41:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1C959610F8 for ; Tue, 7 Sep 2021 17:41:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1C959610F8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B81F6E037; Tue, 7 Sep 2021 17:41:13 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id C185F6E037 for ; Tue, 7 Sep 2021 17:41:10 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10100"; a="305834300" X-IronPort-AV: E=Sophos;i="5.85,274,1624345200"; d="scan'208";a="305834300" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2021 10:41:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,274,1624345200"; d="scan'208";a="449099652" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga002.jf.intel.com with SMTP; 07 Sep 2021 10:41:07 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 07 Sep 2021 20:41:06 +0300 Date: Tue, 7 Sep 2021 20:41:06 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Matt Roper Cc: Ayaz A Siddiqui , intel-gfx@lists.freedesktop.org Message-ID: References: <20210907171639.1221287-1-ayaz.siddiqui@intel.com> <20210907172728.GF461228@mdroper-desk1.amr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210907172728.GF461228@mdroper-desk1.amr.corp.intel.com> X-Patchwork-Hint: comment Subject: Re: [Intel-gfx] [PATCH] drm/i915/gt: Add separate MOCS table for Gen12 devices other than TGL/RKL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Sep 07, 2021 at 10:27:28AM -0700, Matt Roper wrote: > On Tue, Sep 07, 2021 at 10:46:39PM +0530, Ayaz A Siddiqui wrote: > > MOCS table of TGL/RKL has MOCS[1] set to L3_UC. > > While for other gen12 devices we need to set MOCS[1] as L3_WB, > > So adding a new MOCS table for other gen 12 devices eg. ADL. > > > > Fixes: cfbe5291a189 ("drm/i915/gt: Initialize unused MOCS entries with device specific values") > > Cc: Matt Roper > > Signed-off-by: Ayaz A Siddiqui > > Yep, we overlooked that the TGL table still had an explicit entry for > I915_MOCS_PTE and wasn't just using an implicit 'unused_entries' lookup > for MOCS[1]. The new table is the same as the TGL table, just with > I915_MOCS_PTE (1) removed. And just how are people planning on handling display cacheability control without a PTE MOCS entry? Is Mesa/etc. already making all external bos uncached on these platforms just in case we might scan out said bo? > > Looks good to me, > > Reviewed-by: Matt Roper > > > > --- > > drivers/gpu/drm/i915/gt/intel_mocs.c | 41 +++++++++++++++++++++++++--- > > 1 file changed, 37 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c > > index e96afd7beb49..c8d289b00de4 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c > > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c > > @@ -315,6 +315,35 @@ static const struct drm_i915_mocs_entry dg1_mocs_table[] = { > > MOCS_ENTRY(63, 0, L3_1_UC), > > }; > > > > +static const struct drm_i915_mocs_entry gen12_mocs_table[] = { > > + > > + GEN11_MOCS_ENTRIES, > > + /* Implicitly enable L1 - HDC:L1 + L3 + LLC */ > > + MOCS_ENTRY(48, > > + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + /* Implicitly enable L1 - HDC:L1 + L3 */ > > + MOCS_ENTRY(49, > > + LE_1_UC | LE_TC_1_LLC, > > + L3_3_WB), > > + /* Implicitly enable L1 - HDC:L1 + LLC */ > > + MOCS_ENTRY(50, > > + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_1_UC), > > + /* Implicitly enable L1 - HDC:L1 */ > > + MOCS_ENTRY(51, > > + LE_1_UC | LE_TC_1_LLC, > > + L3_1_UC), > > + /* HW Special Case (CCS) */ > > + MOCS_ENTRY(60, > > + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_1_UC), > > + /* HW Special Case (Displayable) */ > > + MOCS_ENTRY(61, > > + LE_1_UC | LE_TC_1_LLC, > > + L3_3_WB), > > +}; > > + > > enum { > > HAS_GLOBAL_MOCS = BIT(0), > > HAS_ENGINE_MOCS = BIT(1), > > @@ -351,14 +380,18 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, > > table->n_entries = GEN9_NUM_MOCS_ENTRIES; > > table->uc_index = 1; > > table->unused_entries_index = 5; > > - } else if (GRAPHICS_VER(i915) >= 12) { > > + } else if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) { > > + /* For TGL/RKL, Can't be changed now for ABI reasons */ > > table->size = ARRAY_SIZE(tgl_mocs_table); > > table->table = tgl_mocs_table; > > table->n_entries = GEN9_NUM_MOCS_ENTRIES; > > table->uc_index = 3; > > - /* For TGL/RKL, Can't be changed now for ABI reasons */ > > - if (!IS_TIGERLAKE(i915) && !IS_ROCKETLAKE(i915)) > > - table->unused_entries_index = 2; > > + } else if (GRAPHICS_VER(i915) >= 12) { > > + table->size = ARRAY_SIZE(gen12_mocs_table); > > + table->table = gen12_mocs_table; > > + table->n_entries = GEN9_NUM_MOCS_ENTRIES; > > + table->uc_index = 3; > > + table->unused_entries_index = 2; > > } else if (GRAPHICS_VER(i915) == 11) { > > table->size = ARRAY_SIZE(icl_mocs_table); > > table->table = icl_mocs_table; > > -- > > 2.26.2 > > > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795 -- Ville Syrjälä Intel