From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCC38C433EF for ; Tue, 19 Oct 2021 10:50:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A11E8610E5 for ; Tue, 19 Oct 2021 10:50:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A11E8610E5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 285ED6E145; Tue, 19 Oct 2021 10:50:56 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id F0C4A6E145 for ; Tue, 19 Oct 2021 10:50:54 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10141"; a="227247656" X-IronPort-AV: E=Sophos;i="5.85,384,1624345200"; d="scan'208";a="227247656" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2021 03:50:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,384,1624345200"; d="scan'208";a="531383600" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga008.fm.intel.com with SMTP; 19 Oct 2021 03:50:51 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 19 Oct 2021 13:50:51 +0300 Date: Tue, 19 Oct 2021 13:50:51 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Jani Nikula Cc: Vandita Kulkarni , intel-gfx@lists.freedesktop.org, imre.deak@intel.com, matthew.d.roper@intel.com Message-ID: References: <20211018065207.30587-1-vandita.kulkarni@intel.com> <20211018065207.30587-2-vandita.kulkarni@intel.com> <875ytts527.fsf@intel.com> <87r1chqpfp.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Patchwork-Hint: comment Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Oct 19, 2021 at 01:41:50PM +0300, Ville Syrjälä wrote: > On Tue, Oct 19, 2021 at 01:28:10PM +0300, Jani Nikula wrote: > > On Tue, 19 Oct 2021, Ville Syrjälä wrote: > > > On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote: > > >> On Mon, 18 Oct 2021, Vandita Kulkarni wrote: > > >> > > >> Commit message goes here. > > >> > > >> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband") > > >> > Signed-off-by: Vandita Kulkarni > > >> > --- > > >> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +- > > >> > drivers/gpu/drm/i915/i915_reg.h | 3 ++- > > >> > 2 files changed, 3 insertions(+), 2 deletions(-) > > >> > > > >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > > >> > index 9ee62707ec72..8c166f92f8bd 100644 > > >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > > >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > > >> > @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) > > >> > if (DISPLAY_VER(i915) == 13) { > > >> > for_each_dsi_port(port, intel_dsi->ports) > > >> > intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), > > >> > - TGL_DSI_CHKN_LSHS_GB, 0x4); > > >> > + TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB_MASK); > > >> > > >> I think you mean the value should be TGL_DSI_CHKN_LSHS_GB. > > > > > > IMO the value should never be named that. It should be > > > TGL_DSI_CHKN_LSHS_GB_. > > > > Alternatively, > > > > #define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, (byte_clocks)) > > > > and > > > > intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), > > TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB(4)); > > > > ? > > > > We're using the value in a specific place that references a w/a, so the > > magic 4 isn't too bad. > > Yeah, for parametrized defines I think the "_" is > not needed. Probably not even desired. The argument passed in > is the "_" essentially. Oh and, yes, I think having the magic number in the code is fine for cases like this. I'd say I probably even prefer it that way. As long as the whole register value isn't a single magic hex constant that I have to decode by hand to see what bitfields are getting what values. -- Ville Syrjälä Intel