From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AEEDC433EF for ; Tue, 19 Oct 2021 12:01:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D3AD610E7 for ; Tue, 19 Oct 2021 12:01:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0D3AD610E7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 65FF66EB98; Tue, 19 Oct 2021 12:01:20 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 823866EB98 for ; Tue, 19 Oct 2021 12:01:19 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10141"; a="227257590" X-IronPort-AV: E=Sophos;i="5.85,384,1624345200"; d="scan'208";a="227257590" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2021 05:01:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,384,1624345200"; d="scan'208";a="574136371" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga002.fm.intel.com with SMTP; 19 Oct 2021 05:01:16 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 19 Oct 2021 15:01:15 +0300 Date: Tue, 19 Oct 2021 15:01:15 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Jani Nikula Cc: Khaled Almahallawy , intel-gfx@lists.freedesktop.org, "Deak, Imre" Message-ID: References: <20210719235927.283173-1-khaled.almahallawy@intel.com> <87bl3lqljk.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <87bl3lqljk.fsf@intel.com> X-Patchwork-Hint: comment Subject: Re: [Intel-gfx] [PATCH] drm/i915/dp: Add missing TPS4 programming bits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Oct 19, 2021 at 02:52:15PM +0300, Jani Nikula wrote: > On Mon, 19 Jul 2021, Khaled Almahallawy wrote: > > Bits 20:19 are used to set CP2520 Patterns 1/2/3 (refer to Specs:50484). > > TPS4 is CP2520 Pattern 3 (refer to DP2.0 spaces Table 3-11, DPCD 00248h > > LINK_QUAL_PATTERN_SELECT, and DP PHY 1.4 CTS - Appendix A - Compliance > > EYE Pattern(CP2520; Normative)) > > > > For TPS4, setting bits 20:19 to value != 00b, leads to a non-TPS4 pattern. > > This is confirmed using DP Scope running DP1.4 PHY CTS. > > > > To avoid any accidental wrong setting of bits 20:19, set it correctly for > > TPS4 LT pattern selection. This programming sequence is the same used by EV. > > Do we need this? I think what we need is some place to initialize DP_TP_CTL fully. Right now it seems to be just all RMW. > > BR, > Jani. > > > > > Cc: Manasi Navare > > Cc: Ville Syrjälä > > CC: José Roberto de Souza > > Cc: Imre Deak > > Signed-off-by: Khaled Almahallawy > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > 2 files changed, 6 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 26a3aa73fcc4..54b4b28fdc74 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -3412,6 +3412,8 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > > break; > > case DP_TRAINING_PATTERN_4: > > temp |= DP_TP_CTL_LINK_TRAIN_PAT4; > > + temp &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; > > + temp |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; > > break; > > } > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 943fe485c662..a65998df9994 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -10176,6 +10176,10 @@ enum skl_power_gate { > > #define DP_TP_CTL_MODE_SST (0 << 27) > > #define DP_TP_CTL_MODE_MST (1 << 27) > > #define DP_TP_CTL_FORCE_ACT (1 << 25) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) > > #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) > > #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) > > #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) > > -- > Jani Nikula, Intel Open Source Graphics Center -- Ville Syrjälä Intel