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Wed, 13 Oct 2021 07:06:12 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:57f4:0:efd0:b9e5:5ae6:c2fa]) by smtp.gmail.com with ESMTPSA id e16sm11711795wrw.17.2021.10.13.07.06.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Oct 2021 07:06:11 -0700 (PDT) Date: Wed, 13 Oct 2021 16:06:10 +0200 From: Daniel Vetter To: Christian =?iso-8859-1?Q?K=F6nig?= Cc: linaro-mm-sig@lists.linaro.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, intel-gfx@lists.freedesktop.org, daniel@ffwll.ch, tvrtko.ursulin@linux.intel.com Message-ID: References: <20211005113742.1101-1-christian.koenig@amd.com> <20211005113742.1101-12-christian.koenig@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20211005113742.1101-12-christian.koenig@amd.com> X-Operating-System: Linux phenom 5.10.0-8-amd64 Subject: Re: [Intel-gfx] [PATCH 11/28] drm/amdgpu: use the new iterator in amdgpu_sync_resv X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Oct 05, 2021 at 01:37:25PM +0200, Christian König wrote: > Simplifying the code a bit. > > Signed-off-by: Christian König Reviewed-by: Daniel Vetter Yeah these iterators rock :-) -Daniel > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 44 ++++++++---------------- > 1 file changed, 14 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c > index 862eb3c1c4c5..f7d8487799b2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c > @@ -252,41 +252,25 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, > struct dma_resv *resv, enum amdgpu_sync_mode mode, > void *owner) > { > - struct dma_resv_list *flist; > + struct dma_resv_iter cursor; > struct dma_fence *f; > - unsigned i; > - int r = 0; > + int r; > > if (resv == NULL) > return -EINVAL; > > - /* always sync to the exclusive fence */ > - f = dma_resv_excl_fence(resv); > - dma_fence_chain_for_each(f, f) { > - struct dma_fence_chain *chain = to_dma_fence_chain(f); > - > - if (amdgpu_sync_test_fence(adev, mode, owner, chain ? > - chain->fence : f)) { > - r = amdgpu_sync_fence(sync, f); > - dma_fence_put(f); > - if (r) > - return r; > - break; > - } > - } > - > - flist = dma_resv_shared_list(resv); > - if (!flist) > - return 0; > - > - for (i = 0; i < flist->shared_count; ++i) { > - f = rcu_dereference_protected(flist->shared[i], > - dma_resv_held(resv)); > - > - if (amdgpu_sync_test_fence(adev, mode, owner, f)) { > - r = amdgpu_sync_fence(sync, f); > - if (r) > - return r; > + dma_resv_for_each_fence(&cursor, resv, true, f) { > + dma_fence_chain_for_each(f, f) { > + struct dma_fence_chain *chain = to_dma_fence_chain(f); > + > + if (amdgpu_sync_test_fence(adev, mode, owner, chain ? > + chain->fence : f)) { > + r = amdgpu_sync_fence(sync, f); > + dma_fence_put(f); > + if (r) > + return r; > + break; > + } > } > } > return 0; > -- > 2.25.1 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch