From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9008C433F5 for ; Thu, 14 Oct 2021 15:43:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 79EA160FDC for ; Thu, 14 Oct 2021 15:43:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 79EA160FDC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5084F6E192; Thu, 14 Oct 2021 15:43:35 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3F3206E183; Thu, 14 Oct 2021 15:43:33 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10137"; a="227600638" X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="227600638" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 08:43:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="626843138" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga001.fm.intel.com with SMTP; 14 Oct 2021 08:43:29 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 14 Oct 2021 18:43:28 +0300 Date: Thu, 14 Oct 2021 18:43:28 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Message-ID: References: <20211014150059.28957-1-jani.nikula@intel.com> <20211014150059.28957-2-jani.nikula@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20211014150059.28957-2-jani.nikula@intel.com> X-Patchwork-Hint: comment Subject: Re: [Intel-gfx] [PATCH 2/3] drm/dp: reuse the 8b/10b link training delay helpers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Oct 14, 2021 at 06:00:58PM +0300, Jani Nikula wrote: > Reuse the 8b/10b link training delay helpers. Functionally this skips > the check for invalid values for DPCD 1.4 and later at clock recovery > delay (as it's a fixed delay and bypasses the rd_interval) but the same > value will be checked and invalid values reported at channel > equalization. > > Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/drm_dp_helper.c | 30 ++++++++++-------------------- > 1 file changed, 10 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index f7ebf5974fa7..ada0a1ff262d 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -284,35 +284,25 @@ EXPORT_SYMBOL(drm_dp_read_channel_eq_delay); > void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > - unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > - DP_TRAINING_AUX_RD_MASK; > + u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > + DP_TRAINING_AUX_RD_MASK; > + int delay_us; > > - if (rd_interval > 4) > - drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n", > - aux->name, rd_interval); > - > - if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) > - rd_interval = 100; > + if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) > + delay_us = 100; > else > - rd_interval *= 4 * USEC_PER_MSEC; > + delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval); > > - usleep_range(rd_interval, rd_interval * 2); > + usleep_range(delay_us, delay_us * 2); > } > EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); > > static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > - unsigned long rd_interval) > + u8 rd_interval) > { > - if (rd_interval > 4) > - drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n", > - aux->name, rd_interval); > - > - if (rd_interval == 0) > - rd_interval = 400; > - else > - rd_interval *= 4 * USEC_PER_MSEC; > + int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval); > > - usleep_range(rd_interval, rd_interval * 2); > + usleep_range(delay_us, delay_us * 2); > } > > void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > -- > 2.30.2 -- Ville Syrjälä Intel