From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3CFCC433F5 for ; Thu, 21 Oct 2021 14:35:39 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BB20460F50 for ; Thu, 21 Oct 2021 14:35:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org BB20460F50 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DA1E26ECA0; Thu, 21 Oct 2021 14:35:38 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id F347E6ECA0; Thu, 21 Oct 2021 14:35:37 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10143"; a="292513422" X-IronPort-AV: E=Sophos;i="5.87,170,1631602800"; d="scan'208";a="292513422" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2021 07:35:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,170,1631602800"; d="scan'208";a="495174359" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga008.jf.intel.com with SMTP; 21 Oct 2021 07:35:33 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 21 Oct 2021 17:35:32 +0300 Date: Thu, 21 Oct 2021 17:35:32 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Ramalingam C Cc: dri-devel , intel-gfx , Daniel Vetter , CQ Tang , Matthew Auld , lucas.demarchi@intel.com, rodrigo.vivi@intel.com, Hellstrom Thomas , Matt Roper , Simon Ser , Pekka Paalanen Message-ID: References: <20211021142627.31058-1-ramalingam.c@intel.com> <20211021142627.31058-15-ramalingam.c@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20211021142627.31058-15-ramalingam.c@intel.com> X-Patchwork-Hint: comment Subject: Re: [Intel-gfx] [PATCH v2 14/17] uapi/drm/dg2: Format modifier for DG2 unified compression and clear color X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Oct 21, 2021 at 07:56:24PM +0530, Ramalingam C wrote: > From: Matt Roper > > DG2 unifies render compression and media compression into a single > format for the first time. The programming and buffer layout is > supposed to match compression on older gen12 platforms, but the > actual compression algorithm is different from any previous platform; as > such, we need a new framebuffer modifier to represent buffers in this > format, but otherwise we can re-use the existing gen12 compression driver > logic. > > DG2 clear color render compression uses Tile4 layout. Therefore, we need > to define a new format modifier for uAPI to support clear color rendering. > > Signed-off-by: Matt Roper > Signed-off-by: Mika Kahola (v2) > Signed-off-by: Juha-Pekka Heikkilä > Signed-off-by: Ramalingam C > cc: Simon Ser > Cc: Pekka Paalanen > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 ++ > .../drm/i915/display/intel_display_types.h | 10 +++- > drivers/gpu/drm/i915/display/intel_fb.c | 7 +++ > .../drm/i915/display/skl_universal_plane.c | 49 +++++++++++++++++-- > include/uapi/drm/drm_fourcc.h | 30 ++++++++++++ > 5 files changed, 94 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 9b678839bf2b..2949fe9f5b9f 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -1013,6 +1013,9 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) > cmd->pixel_format); > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > + case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS: > + case I915_FORMAT_MOD_F_TILED_DG2_MC_CCS: > + case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC: > return lookup_format_info(gen12_ccs_formats, > ARRAY_SIZE(gen12_ccs_formats), > cmd->pixel_format); That seems not right. Flat CCS is invisible to the user so the format info should not include a CCS plane. -- Ville Syrjälä Intel