From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21620C433EF for ; Mon, 15 Nov 2021 18:46:51 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E3CC4635E8 for ; Mon, 15 Nov 2021 18:46:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E3CC4635E8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F95A6E879; Mon, 15 Nov 2021 18:46:45 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 30B586E874; Mon, 15 Nov 2021 18:46:43 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10169"; a="296933612" X-IronPort-AV: E=Sophos;i="5.87,237,1631602800"; d="scan'208";a="296933612" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Nov 2021 10:46:42 -0800 X-IronPort-AV: E=Sophos;i="5.87,237,1631602800"; d="scan'208";a="506043314" Received: from rakeshr1-mobl1.amr.corp.intel.com (HELO intel.com) ([10.255.37.176]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Nov 2021 10:46:42 -0800 Date: Mon, 15 Nov 2021 13:46:40 -0500 From: Rodrigo Vivi To: Matt Roper Message-ID: References: <20211112160107.1593906-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211112160107.1593906-1-matthew.d.roper@intel.com> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Don't read query SSEU for non-existent slice 0 on old platforms X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Nov 12, 2021 at 08:01:07AM -0800, Matt Roper wrote: > Pre-HSW platforms don't use the gt SSEU structures; this means that > calling intel_sseu_get_subslices() on slice 0 for these platforms will > trip a GEM_BUG_ON(slice >= sseu->max_slices) warning. > > Let's move the DSS lookup for a DG2 workaround into a helper function > that will only get called after we've already decided that we're on a > DG2 platform. > > Fixes: 645cc0b9d972 ("drm/i915/dg2: Add initial gt/ctx/engine workarounds") > Signed-off-by: Matt Roper Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 51591119da15..a9727447c037 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2019,11 +2019,18 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > CMD_CCTL_MOCS_OVERRIDE(mocs, mocs)); > } > } > + > +static bool needs_wa_1308578152(struct intel_engine_cs *engine) > +{ > + u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0); > + > + return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0; > +} > + > static void > rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > { > struct drm_i915_private *i915 = engine->i915; > - u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0); > > if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { > /* Wa_14013392000:dg2_g11 */ > @@ -2057,7 +2064,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > > /* Wa_1308578152:dg2_g10 when first gslice is fused off */ > if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_C0) && > - (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0) { > + needs_wa_1308578152(engine)) { > wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, > GEN12_REPLAY_MODE_GRANULARITY); > } > -- > 2.33.0 >