[Intel-gfx] [PATCH 10/14] drm/i915: Program FDI RX TUSIZE2

Ville Syrjala
2022-01-27T09:33:48Z

When using the refresh rate swithching with FDI we must program
RXTUSIZE2 in addition to RXTUSIZE1.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fdi.c | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index fdbeaf6f38f4..4b634c1d2837 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -381,6 +381,8 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
*/
intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+ intel_de_write(dev_priv, FDI_RX_TUSIZE2(pipe),
+ intel_de_read(dev_priv, PIPE_DATA_M2(pipe)) & TU_SIZE_MASK);

/* FDI needs bits from pipe first */
assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder);
@@ -491,6 +493,8 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
*/
intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+ intel_de_write(dev_priv, FDI_RX_TUSIZE2(pipe),
+ intel_de_read(dev_priv, PIPE_DATA_M2(pipe)) & TU_SIZE_MASK);

/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
for train result */
@@ -637,6 +641,8 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
*/
intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+ intel_de_write(dev_priv, FDI_RX_TUSIZE2(pipe),
+ intel_de_read(dev_priv, PIPE_DATA_M2(pipe)) & TU_SIZE_MASK);

/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
for train result */
--
2.34.1