From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A04D7C433FE for ; Tue, 22 Feb 2022 22:35:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 14C2410E5A8; Tue, 22 Feb 2022 22:35:40 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3CCBF10E3B3; Tue, 22 Feb 2022 22:35:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645569338; x=1677105338; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=UgejPx51ToloZZZLUuw++UN2w5kytsuGlJTnOx1RrFc=; b=EzWPqg//Q0b1y2Ei7mRWgmu30le47OsyhwMs8A7aTa398F0sZxmspJN+ NJSXlc2EZXiiTibqbwgXn0v10AUkAqjWqPX+bxoI61oqkXgUA2GXTcDk4 LklTFfVRV1H2syArY84meNlm2EP5Y4T/H813EKiQ2QR4AIF6FdkgNAJ9H eF5UnZBuVeAs7J5ZK1Ji68bpwXQELloj4do2wNBCE/iCR/M1YiyqlsyTd vZhk4oGoNs2t60D4Wc7vIbz1ofGIJhE/H5S23+AGtn5WbiwiehJE3Ehtk A5RAF7RlA8SXNrB+ZYFW/HvZX2YTjuIfrhV0kxi60iDir2RDGhVY7Lhcw w==; X-IronPort-AV: E=McAfee;i="6200,9189,10266"; a="232452172" X-IronPort-AV: E=Sophos;i="5.88,389,1635231600"; d="scan'208";a="232452172" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2022 14:35:37 -0800 X-IronPort-AV: E=Sophos;i="5.88,389,1635231600"; d="scan'208";a="637187120" Received: from mdroper-desk1.fm.intel.com (HELO mdroper-desk1.amr.corp.intel.com) ([10.1.27.134]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2022 14:35:37 -0800 Date: Tue, 22 Feb 2022 14:35:36 -0800 From: Matt Roper To: Michael Cheng Message-ID: References: <20220210183636.1187973-1-michael.cheng@intel.com> <20220210183636.1187973-5-michael.cheng@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220210183636.1187973-5-michael.cheng@intel.com> Subject: Re: [Intel-gfx] [PATCH v10 4/6] drm/i915/gt: Re-work reset_csb X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Feb 10, 2022 at 10:36:34AM -0800, Michael Cheng wrote: > Use drm_clflush_virt_range instead of directly invoking clflush. This > will prevent compiler errors when building for non-x86 architectures. > > v2(Michael Cheng): Remove extra clflush > > v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range > takes care of it. > > Signed-off-by: Michael Cheng > --- > drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > index 6186a5e4b191..11b864fd68a5 100644 > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > @@ -2945,9 +2945,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive) > { > struct intel_engine_execlists * const execlists = &engine->execlists; > > - mb(); /* paranoia: read the CSB pointers from after the reset */ > - clflush(execlists->csb_write); > - mb(); > + drm_clflush_virt_range(execlists->csb_write, > + sizeof(execlists->csb_write)); I think you technically want sizeof(execlists->csb_write[0]) here, right? I.e., the size of the value (32-bits), not the size of the pointer (32 or 64 depending on architecture). Not that it will really change the behavior since it all works out to a single cacheline in the end. Aside from that, Reviewed-by: Matt Roper > > inactive = process_csb(engine, inactive); /* drain preemption events */ > > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795