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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?/U+RwlHJI+aUIE6g5oSQUr4Jm3rwzyAbHBDUVyfqCvmk/1yiKEbe8PRtgw1M?= =?us-ascii?Q?tnfwEVDKLGZW8MLX/B2QK4QkLlxjFb4diqorSaZfABwR9xY7qAoeEarWdXI/?= =?us-ascii?Q?zZPa2qZRlYHU0ige+wmxq0LJw0Gvw4sWxfLQoQ0wjqLY/6It6ilDTvi/UC5+?= =?us-ascii?Q?K+QLEnIa2fwK9dQBmbl7BpWmF3ktrutZv0gJHWLg6uZ9J8kRoAABBGLS42nM?= =?us-ascii?Q?okLqQqD266400KMNK07z+9SeB3303rJJ6XbZyYBSgs9Q0UF7C/V7U4HFI6pV?= =?us-ascii?Q?5DeTsljFK2QvMYpqjDUmCR8NcNA91TEcCfc3wgaz2DV9uyKQ/XD3qqHWiXKX?= =?us-ascii?Q?f2EBiviE/hb6nl3nFN1LqdAmvhs2P6WfNs9npGEPhuuZJUSl/6YdT7AnkRGg?= =?us-ascii?Q?H6Sd3F/T2q4zIOxlquKKD8BC3fHFYeC/4eXWGXNzanutXkt28ahxZtDqnf71?= =?us-ascii?Q?DyLXFFxxTwMYpN0BnWoK/Ct4wWLGtQkVgL3VXi2L1QSN8HMpRpSlRG074tIv?= =?us-ascii?Q?TbCL/uITvRyTU3wfkNDjbBHHY7yWLEh+CTVe2kVGPPEefrFFO/qr2LUUttal?= =?us-ascii?Q?JwlLuBd6NSyHpNrrhm7cOCGJ8ypP/Jvlsa4wcVs1MqASnxDr0Rbz4kq95h7x?= =?us-ascii?Q?TeQx6u3f9d7kuO8UhiGrfz3/OyXd3FYtCFWn3+yUgaA1Bpx47cENd23/DT6f?= =?us-ascii?Q?ZjFPbUxcQCv3yLteQ0EFstpK2D1hBmJxlqTJGjoZye7USH2D25jY8Hpljpc4?= =?us-ascii?Q?eMnesgRiYrBGO6qWGdbYJE1jMWdHrlhJ6E1IYpLt2/EjxcjO0DtFvHqsOEcu?= =?us-ascii?Q?h3qB2nIJWAcIW9RSXEq1VMnF+3e7i+UBmwVU83bbpCWGUEG3/yqNEFmauhpF?= =?us-ascii?Q?oAspSLRCcwltVX6C3kzeVxMU6JfUSFoTbfJUmEdMCPPlpBmvW9Q8+BBf1QSG?= =?us-ascii?Q?9z58yDv1xxLKbaoquIy2z2/gj5fs1tGMnQqInEELeYbAE+6kqvEzduvLp2Zg?= =?us-ascii?Q?QrvxtqKTjJcydRzU/6NTZxGnpZrCUBjw3yh1U3b2hi3cXqMIgZwLAMBBSaWz?= =?us-ascii?Q?CV6OAaEIwLS78B5CHYGjA1N9s6V4W6f4dtqLzb4FdcoQ3kAq/rTpGyBq+eQx?= =?us-ascii?Q?DG7FHFHx4GMI1uYeZu+XKU4oZRKXD8whFYX7qJTKKOO+cX1TtBl0lWQ922VE?= =?us-ascii?Q?w0H8PPd5BNOF/+DB70k/qje5p4TiVT5NWnwcxlAUKo3b4+YPuPAX2awOwWMb?= =?us-ascii?Q?3ArSysz7S+n1QYzohK6xtMrPIjMpWsUeLKwbdWvxpWJGRWKqACScIMDbyU+2?= =?us-ascii?Q?NxwhpQhOEY/MnC6SIJ5pzXFRWexVeaV71GUN2LhXu+kMNMoJtX11xrZbQk9b?= =?us-ascii?Q?Kl0HVoR+XK0hzg3bIZ9VK2wn22tM6TQcRoi0qb3Hu5svgiv+T6IQKDo4YZg7?= =?us-ascii?Q?Dx5Tce4pgpZD0d4iMD5W/Ad6YhqSkArFVYJ4sn5AUTVrJsOh1YENokP5ocnh?= =?us-ascii?Q?Lp2yNDPcF2ps6BPyPelKI4bPH2z5NpOaVAi3JIFJyiX6EhPXq4szTlNtqjHl?= =?us-ascii?Q?+4T0dv6UEwNXK77ICH24Lk3nLUXXS/lThDM3avItKWl+7DglgBeBp2oaW4Cu?= =?us-ascii?Q?7g=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 44b5be76-402f-4239-be3a-08da60efeb78 X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6059.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2022 14:41:20.0509 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZV8Q2RNL4nhpDonoXtBbCa5EgyIfJhWa193E5jIeMITz/It3RG0xBbipvKwO7wcN5mFVoOsKYEumWSq1np1ABw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB3372 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/gem: Look for waitboosting across the whole object prior to individual waits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Voegtle , intel-gfx@lists.freedesktop.org, Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Jul 08, 2022 at 04:20:11PM +0200, Karolina Drobnik wrote: > From: Chris Wilson > > We employ a "waitboost" heuristic to detect when userspace is stalled > waiting for results from earlier execution. Under latency sensitive work > mixed between the gpu/cpu, the GPU is typically under-utilised and so > RPS sees that low utilisation as a reason to downclock the frequency, > causing longer stalls and lower throughput. The user left waiting for > the results is not impressed. > > On applying commit 047a1b877ed4 ("dma-buf & drm/amdgpu: remove dma_resv > workaround") it was observed that deinterlacing h264 on Haswell > performance dropped by 2-5x. The reason being that the natural workload > was not intense enough to trigger RPS (using HW evaluation intervals) to > upclock, and so it was depending on waitboosting for the throughput. > > Commit 047a1b877ed4 ("dma-buf & drm/amdgpu: remove dma_resv workaround") > changes the composition of dma-resv from keeping a single write fence + > multiple read fences, to a single array of multiple write and read > fences (a maximum of one pair of write/read fences per context). The > iteration order was also changed implicitly from all-read fences then > the single write fence, to a mix of write fences followed by read > fences. It is that ordering change that belied the fragility of > waitboosting. > > Currently, a waitboost is inspected at the point of waiting on an > outstanding fence. If the GPU is backlogged such that we haven't yet > stated the request we need to wait on, we force the GPU to upclock until > the completion of that request. By changing the order in which we waited > upon requests, we ended up waiting on those requests in sequence and as > such we saw that each request was already started and so not a suitable > candidate for waitboosting. > > Instead of asking whether to boost each fence in turn, we can look at > whether boosting is required for the dma-resv ensemble prior to waiting > on any fence, making the heuristic more robust to the order in which > fences are stored in the dma-resv. > > Reported-by: Thomas Voegtle > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6284 > Fixes: 047a1b877ed4 ("dma-buf & drm/amdgpu: remove dma_resv workaround") > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin > Signed-off-by: Karolina Drobnik > Tested-by: Thomas Voegtle > Reviewed-by: Andi Shyti Acked-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/gem/i915_gem_wait.c | 34 ++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c b/drivers/gpu/drm/i915/gem/i915_gem_wait.c > index 319936f91ac5..e6e01c2a74a6 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c > @@ -9,6 +9,7 @@ > #include > > #include "gt/intel_engine.h" > +#include "gt/intel_rps.h" > > #include "i915_gem_ioctls.h" > #include "i915_gem_object.h" > @@ -31,6 +32,37 @@ i915_gem_object_wait_fence(struct dma_fence *fence, > timeout); > } > > +static void > +i915_gem_object_boost(struct dma_resv *resv, unsigned int flags) > +{ > + struct dma_resv_iter cursor; > + struct dma_fence *fence; > + > + /* > + * Prescan all fences for potential boosting before we begin waiting. > + * > + * When we wait, we wait on outstanding fences serially. If the > + * dma-resv contains a sequence such as 1:1, 1:2 instead of a reduced > + * form 1:2, then as we look at each wait in turn we see that each > + * request is currently executing and not worthy of boosting. But if > + * we only happen to look at the final fence in the sequence (because > + * of request coalescing or splitting between read/write arrays by > + * the iterator), then we would boost. As such our decision to boost > + * or not is delicately balanced on the order we wait on fences. > + * > + * So instead of looking for boosts sequentially, look for all boosts > + * upfront and then wait on the outstanding fences. > + */ > + > + dma_resv_iter_begin(&cursor, resv, > + dma_resv_usage_rw(flags & I915_WAIT_ALL)); > + dma_resv_for_each_fence_unlocked(&cursor, fence) > + if (dma_fence_is_i915(fence) && > + !i915_request_started(to_request(fence))) > + intel_rps_boost(to_request(fence)); > + dma_resv_iter_end(&cursor); > +} > + > static long > i915_gem_object_wait_reservation(struct dma_resv *resv, > unsigned int flags, > @@ -40,6 +72,8 @@ i915_gem_object_wait_reservation(struct dma_resv *resv, > struct dma_fence *fence; > long ret = timeout ?: 1; > > + i915_gem_object_boost(resv, flags); > + > dma_resv_iter_begin(&cursor, resv, > dma_resv_usage_rw(flags & I915_WAIT_ALL)); > dma_resv_for_each_fence_unlocked(&cursor, fence) { > -- > 2.25.1 >