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* [Intel-gfx] [PATCH 1/3] drm/i915: Remove redundant check for DG1
@ 2023-03-06 20:49 Lucas De Marchi
  2023-03-06 20:49 ` [Intel-gfx] [PATCH 2/3] drm/i915: Move DG2 tuning to the right function Lucas De Marchi
                   ` (5 more replies)
  0 siblings, 6 replies; 12+ messages in thread
From: Lucas De Marchi @ 2023-03-06 20:49 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi, dri-devel

dg1_gt_workarounds_init() is only ever called for DG1, so there is no
point checking it again.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 32aa1647721a..eb6cc4867d67 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1472,21 +1472,15 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 static void
 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-	struct drm_i915_private *i915 = gt->i915;
-
 	gen12_gt_workarounds_init(gt, wal);
 
 	/* Wa_1409420604:dg1 */
-	if (IS_DG1(i915))
-		wa_mcr_write_or(wal,
-				SUBSLICE_UNIT_LEVEL_CLKGATE2,
-				CPSSUNIT_CLKGATE_DIS);
+	wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2,
+			CPSSUNIT_CLKGATE_DIS);
 
 	/* Wa_1408615072:dg1 */
 	/* Empirical testing shows this register is unaffected by engine reset. */
-	if (IS_DG1(i915))
-		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
-			    VSUNIT_CLKGATE_DIS_TGL);
+	wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
 }
 
 static void
-- 
2.39.0


^ permalink raw reply related	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2023-03-13 13:33 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-03-06 20:49 [Intel-gfx] [PATCH 1/3] drm/i915: Remove redundant check for DG1 Lucas De Marchi
2023-03-06 20:49 ` [Intel-gfx] [PATCH 2/3] drm/i915: Move DG2 tuning to the right function Lucas De Marchi
2023-03-06 23:16   ` Matt Roper
2023-03-06 20:49 ` [Intel-gfx] [PATCH 3/3] drm/i915/dg1: Move Wa_1806527549 " Lucas De Marchi
2023-03-06 23:17   ` Matt Roper
2023-03-06 23:53     ` Lucas De Marchi
2023-03-06 23:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Remove redundant check for DG1 Patchwork
2023-03-06 23:15 ` [Intel-gfx] [PATCH 1/3] " Matt Roper
2023-03-07 12:01 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] " Patchwork
2023-03-13  9:10 ` [Intel-gfx] [PATCH 1/3] " Ville Syrjälä
2023-03-13 13:23   ` Lucas De Marchi
2023-03-13 13:32     ` Ville Syrjälä

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