From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB5C7C6FD1C for ; Thu, 23 Mar 2023 17:08:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 126FA10E0CA; Thu, 23 Mar 2023 17:08:33 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0485510E0CA for ; Thu, 23 Mar 2023 17:08:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679591310; x=1711127310; h=date:from:to:cc:subject:message-id:reply-to:references: mime-version:in-reply-to; bh=mt4jCCOP5GDj9FD9ufeCb9hNqLCtXzE6JJRP6uBk5GA=; b=ereFeuJ16s15MFors/jm+tSFaEYNC0RIOMXsN8WY6qyxAzfb2sxrGHjh VHON9Il6wPBMsfeJ+UUnXvJzSXtkFKKUeFEdz2JciGHVIzjwNOi2SaTup RNQZokFzUTeuwIXXLKOVS4JqUZzx1yBzjHlsmxX9+ZKT/pCB/l6nPehb2 GF9dzeU8qzW33C+3Bz4JgN91fzvmL2lNS4sbvW1nszaH6ZHgR7ctHQdrX VZ+9IVfRNbbwhUp+3IRYLzLP86YsvLRWleK6IFxlOc+wF41luSJzu66B9 /noUwc2BtJOOtYJgLQ2Iwisw7UIFYM/hINEqSQW/2YR97hW2jTYRNLVkp g==; X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="338281627" X-IronPort-AV: E=Sophos;i="5.98,285,1673942400"; d="scan'208";a="338281627" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 10:08:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="659695434" X-IronPort-AV: E=Sophos;i="5.98,285,1673942400"; d="scan'208";a="659695434" Received: from ideak-desk.fi.intel.com ([10.237.72.58]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 10:08:28 -0700 Date: Thu, 23 Mar 2023 19:08:24 +0200 From: Imre Deak To: Jani Nikula Message-ID: References: <20230323142035.1432621-1-imre.deak@intel.com> <20230323142035.1432621-21-imre.deak@intel.com> <87sfdv5ygd.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87sfdv5ygd.fsf@intel.com> Subject: Re: [Intel-gfx] [PATCH 20/29] drm/i915/tc: Add asserts in TC PHY hooks that the required power is on X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: imre.deak@intel.com Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Mar 23, 2023 at 04:33:54PM +0200, Jani Nikula wrote: > On Thu, 23 Mar 2023, Imre Deak wrote: > > Add an assert to each TC PHY hook that their required power domain is > > enabled. > > > > While at it add a comment describing the domains used on each platform > > and TC mode. > > > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/display/intel_tc.c | 61 +++++++++++++++++++++++++ > > 1 file changed, 61 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c > > index e68346c5e6036..7bcd93f1f0597 100644 > > --- a/drivers/gpu/drm/i915/display/intel_tc.c > > +++ b/drivers/gpu/drm/i915/display/intel_tc.c > > @@ -111,6 +111,46 @@ bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port) > > return intel_tc_port_in_mode(dig_port, TC_PORT_LEGACY); > > } > > > > +/** > > This also shouldn't be a kernel-doc comment. Ok, will change these. > > BR, > Jani. > > > + * The display power domains used for TC ports depending on the > > + * platform and TC mode (legacy, DP-alt, TBT): > > + * > > + * POWER_DOMAIN_DISPLAY_CORE: > > + * -------------------------- > > + * ADLP/all modes: > > + * - TCSS/IOM access for PHY ready state. > > + * ADLP+/all modes: > > + * - DE/north-,south-HPD ISR access for HPD live state. > > + * > > + * POWER_DOMAIN_PORT_DDI_LANES_: > > + * ----------------------------------- > > + * ICL+/all modes: > > + * - DE/DDI_BUF access for port enabled state. > > + * ADLP/all modes: > > + * - DE/DDI_BUF access for PHY owned state. > > + * > > + * POWER_DOMAIN_AUX_USBC: > > + * ------------------------------------- > > + * ICL/legacy mode: > > + * - TCSS/IOM,FIA access for PHY ready, owned and HPD live state > > + * - TCSS/PHY: block TC-cold power state for using the PHY AUX and > > + * main lanes. > > + * ADLP/legacy, DP-alt modes: > > + * - TCSS/PHY: block TC-cold power state for using the PHY AUX and > > + * main lanes. > > + * > > + * POWER_DOMAIN_TC_COLD_OFF: > > + * ------------------------- > > + * TGL/legacy, DP-alt modes: > > + * - TCSS/IOM,FIA access for PHY ready, owned and HPD live state > > + * - TCSS/PHY: block TC-cold power state for using the PHY AUX and > > + * main lanes. > > + * > > + * ICL, TGL, ADLP/TBT mode: > > + * - TCSS/IOM,FIA access for HPD live state > > + * - TCSS/TBT: block TC-cold power state for using the (TBT DP-IN) > > + * AUX and main lanes. > > + */ > > bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port) > > { > > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > @@ -163,6 +203,15 @@ tc_cold_unblock(struct intel_tc_port *tc, intel_wakeref_t wakeref) > > __tc_cold_unblock(tc, domain, wakeref); > > } > > > > +static void > > +assert_display_core_power_enabled(struct intel_tc_port *tc) > > +{ > > + struct drm_i915_private *i915 = tc_to_i915(tc); > > + > > + drm_WARN_ON(&i915->drm, > > + !intel_display_power_is_enabled(i915, POWER_DOMAIN_DISPLAY_CORE)); > > +} > > + > > static void > > assert_tc_cold_blocked(struct intel_tc_port *tc) > > { > > @@ -378,6 +427,8 @@ static bool icl_tc_phy_is_ready(struct intel_tc_port *tc) > > struct drm_i915_private *i915 = tc_to_i915(tc); > > u32 val; > > > > + assert_tc_cold_blocked(tc); > > + > > val = intel_de_read(i915, PORT_TX_DFLEXDPPMS(tc->phy_fia)); > > if (val == 0xffffffff) { > > drm_dbg_kms(&i915->drm, > > @@ -395,6 +446,8 @@ static bool icl_tc_phy_take_ownership(struct intel_tc_port *tc, > > struct drm_i915_private *i915 = tc_to_i915(tc); > > u32 val; > > > > + assert_tc_cold_blocked(tc); > > + > > val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(tc->phy_fia)); > > if (val == 0xffffffff) { > > drm_dbg_kms(&i915->drm, > > @@ -418,6 +471,8 @@ static bool icl_tc_phy_is_owned(struct intel_tc_port *tc) > > struct drm_i915_private *i915 = tc_to_i915(tc); > > u32 val; > > > > + assert_tc_cold_blocked(tc); > > + > > val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(tc->phy_fia)); > > if (val == 0xffffffff) { > > drm_dbg_kms(&i915->drm, > > @@ -626,6 +681,8 @@ static bool adlp_tc_phy_is_ready(struct intel_tc_port *tc) > > enum tc_port tc_port = intel_port_to_tc(i915, tc->dig_port->base.port); > > u32 val; > > > > + assert_display_core_power_enabled(tc); > > + > > val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); > > if (val == 0xffffffff) { > > drm_dbg_kms(&i915->drm, > > @@ -643,6 +700,8 @@ static bool adlp_tc_phy_take_ownership(struct intel_tc_port *tc, > > struct drm_i915_private *i915 = tc_to_i915(tc); > > enum port port = tc->dig_port->base.port; > > > > + assert_tc_port_power_enabled(tc); > > + > > intel_de_rmw(i915, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP, > > take ? DDI_BUF_CTL_TC_PHY_OWNERSHIP : 0); > > > > @@ -655,6 +714,8 @@ static bool adlp_tc_phy_is_owned(struct intel_tc_port *tc) > > enum port port = tc->dig_port->base.port; > > u32 val; > > > > + assert_tc_port_power_enabled(tc); > > + > > val = intel_de_read(i915, DDI_BUF_CTL(port)); > > return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP; > > } > > -- > Jani Nikula, Intel Open Source Graphics Center