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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?pufcd+cctJUYpAUTstd3cb1U+ktwxJkffRLnicIfhMrXhwDDpOlEObB508Rp?= =?us-ascii?Q?jf4x0IMTlUeZG47ySGIK+TN4dUIDYK9YJefEYAIUPJE1V5s1xa9A+flodVnW?= =?us-ascii?Q?jw2mwHyxoRXwroe41pnytueicoT7eWxLgN2wV6+VGIoCoF60t708BsOm5pN4?= =?us-ascii?Q?KioqDGDxefyshMcVjkAi8kg9A1KONBN7psV2GwRWYiC4irNEZAY8qobKdHrU?= =?us-ascii?Q?dDIa1fj3r2JmC1WjzfJ929BdBgfDqHuEPZ/AZVZ+clp+2GH92ZJK9PmCCA1k?= =?us-ascii?Q?f0F3e5D6kRkqbkzxbQ5you6uMELgU9deKbCgzmyXQcPsHk5gNzVGqcXg72ZB?= =?us-ascii?Q?CqEAMUy+mJzd2j+p06kd9VYxL3eyE0AghPPlFu4xh4vclBl/eN6N3oOcCxRX?= =?us-ascii?Q?V/PtLb5XtGbl3dUTPy7iAy+nELLNSDDVQbYOznNRQAXgpTDcOW3NyPM/MB1z?= =?us-ascii?Q?QGb31TlgT9a9QCTCBZ3+NFhq+1pVQlpMktNlDOw2bdAiJ411BR1oZfRMaVuD?= =?us-ascii?Q?lnTxWYcNxZBkU4NWWuQDxJWBaToevOwvx8Mpzs/UglJgro0BnTsVt7ISOo4m?= =?us-ascii?Q?jGF/2fkKd29NLzkikjNCIb0rXeKJLw7ZqOwoFvOXJCOQ0XpKYyL2ZJxPoDgB?= =?us-ascii?Q?XZHYs14Afr1o3aVjHe83ECncBfdk0NJqml7VtYx0VpQM8CPS2ljkGcMUGNRP?= =?us-ascii?Q?B3xLlYU5obm1hV9I/Gd4/heZytRljaaOSrfU1FWzSwNllBGk6fiv0sxrP+gk?= =?us-ascii?Q?mm4johkzHXWtClYPP38qmoitJkUyJT29212fbAR/y8NkPzCxEuNhm23qNvbv?= =?us-ascii?Q?WeFVZWQ3FrzW9nlG+4SozPuiINUNo6hJdZIDUZKThfrv5n9luqjSX+1RjChi?= =?us-ascii?Q?ew+mg2ZJQ+1mesIibdjx1TiirguxJFPVbmIlWPGEhBkPkdX9nJeVv6DwGHTm?= =?us-ascii?Q?jkbv98lfmgiacq3A1TJqj5QXyyQQJZgof3YE4BGpb/tTI5mM/8GuQxm1iZlg?= =?us-ascii?Q?gQXO8ept0e1HTN7m0KmbROyzgw9qShuP8X6G59mTGA0Q1Nuj5l/iLKhcpxdE?= =?us-ascii?Q?oaFTbo3GLKgeaN3ZBfzMfgw98zD8dqmiTH6BZkXYN67JYpyuZ3e3aUFu5xJz?= =?us-ascii?Q?34hKPklNM4DeMHyfF9XYXLRa2zPzvM7BdzzHMTwPBWm8eJTKmVSIOsvjvxeU?= =?us-ascii?Q?kIixxvZogcWfApwBlRoNymmB1Tig3/S5BL4JJC4gXMDPGpdzdBQwVuCmNOP4?= =?us-ascii?Q?I+x+Koxr+2DJ1EdUGGeCjD3fynHPtkW9UshNpespKMWNziMXEDPSDq531St3?= =?us-ascii?Q?qsfSP9aIP5RZOYKlPZZkH9Xn0jDy7E0NCCO9av89erp9j0XBar23fSrUESny?= =?us-ascii?Q?Ts+H7SqAf3tuVV+LEe7f9kHfPR1F7ju8zTuRhH7kzhCd7Be8JKYzuS/GamNM?= =?us-ascii?Q?fTZCSDnnZlF30/G8l8O9yF81MDEfmmpNXTCQmSK73aJgG12KegZVRmDW00yR?= =?us-ascii?Q?HceJSqgMwKlPnQb6bfg/7uyn2f0eUZeEDuCfxxGov/1SZN0/m1O6s6Fzu6Al?= =?us-ascii?Q?2SFVetNz9/FiEEogh2LkUBDogDib0GCFF6inHzhZ?= X-MS-Exchange-CrossTenant-Network-Message-Id: 6c980b1c-1fdd-4ce2-5037-08db35ddbc5d X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6059.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Apr 2023 13:57:47.0877 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KmZy+7OeQMle9tzX3XxmOec7VZ8LUni6lnzKj1Z8bOEQoOS/7SJJiwN3wRkJ1jWrMvfDWQBQ2nbLx8GBrGh2yA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR11MB6536 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH] i915/guc/slpc: Provide sysfs for efficient freq X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Mar 31, 2023 at 08:11:29PM -0700, Dixit, Ashutosh wrote: > On Fri, 31 Mar 2023 19:00:49 -0700, Vinay Belgaumkar wrote: > > > > Hi Vinay, > > > @@ -478,20 +507,15 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val) > > val > slpc->max_freq_softlimit) > > return -EINVAL; > > > > + /* Ignore efficient freq if lower min freq is requested */ > > + ret = intel_guc_slpc_set_ignore_eff_freq(slpc, val < slpc->rp1_freq); > > + if (ret) > > + goto out; > > + > > I don't agree with this. If we are now providing an interface explicitly to > ignore RPe, that should be /only/ way to ignore RPe. There should be no > other "under the hood" ignoring of RPe. In other words, ignoring RPe should > be minimized unless explicitly requested. > > I don't clearly understand why this was done previously but it makes even > less sense to me now after this patch. well, I had suggested this previously. And just because without this we would be breaking API expectations. When user selects a minimal frequency it expect that to stick. But with the efficient freq enabled in guc if minimal is less than the efficient one, this request is likely ignored. Well, even worse is that we are actually caching the request in the soft values. So we show a minimal, but the hardware without any workload is operating at efficient. So, the thought process was: 'if user requested a very low minimal, we give them the minimal requested, even if that means to disable the efficient freq.' So, that was introduced to avoid API breakage. Removing it now would mean breaking API. (Not sure if the IGT tests for the API got merged already, but think that as the API contract). But I do agree with you that having something selected from multiple places also has the potential to cause some miss-expectations. So I was thinking about multiple even orders where the user select the RP0 as minimal, then enable the efficient or vice versa, but I couldn't think of a bad case. Or at least not as bad as the user asking to get RP0 as minimal and only getting RPe back. With this in mind, and having checked the code: Reviewed-by: Rodrigo Vivi But I won't push this immediately because I'm still open to hear another side/angle. > > Thanks. > -- > Ashutosh > > > > /* Need a lock now since waitboost can be modifying min as well */ > > mutex_lock(&slpc->lock); > > wakeref = intel_runtime_pm_get(&i915->runtime_pm); > > > > - /* Ignore efficient freq if lower min freq is requested */ > > - ret = slpc_set_param(slpc, > > - SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY, > > - val < slpc->rp1_freq); > > - if (ret) { > > - guc_probe_error(slpc_to_guc(slpc), "Failed to toggle efficient freq: %pe\n", > > - ERR_PTR(ret)); > > - goto out; > > - } > > - > > ret = slpc_set_param(slpc, > > SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ, > > val);