From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46EE9C77B71 for ; Tue, 18 Apr 2023 10:10:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 89CC210E73F; Tue, 18 Apr 2023 10:10:48 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C9CE10E73F for ; Tue, 18 Apr 2023 10:10:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681812646; x=1713348646; h=date:from:to:cc:subject:message-id:reply-to:references: mime-version:in-reply-to; bh=kci+MFe3NRQKsxY+4835cB2+Uhdf5/Muin+6Yg9nSBI=; b=ji+LlwfqIIk79+5NmLh5e/aPVH5kMCd2/iMIlCmdtpq+13UzrxwLQtxc soDKZpb9EJqiSFrUukopXxt73GMBXgs+Wpuk9KUKAWrer8l4U9xvuh4WM 1PSvLLEtwkSMZRWvzyLxksCGI1MbktmfHQD3n6vjwZLy8ExQLYTa3M8on rCnHUThK1SmaOdpB2xeuD1/j986wGYH/I5Vx8sdA8ISQj9NKpvREANs/7 Ru3wDz6daGgJvevHbt2IHmc2bko4QLXxKjCW8OeQbgQYMJ0R6sBf8OCEx wI+C5Yl3IL9KiaNphlIrdWmvBrkm7hGtV0Eovn+8hq3g/K5dil0pse9bN w==; X-IronPort-AV: E=McAfee;i="6600,9927,10683"; a="333933319" X-IronPort-AV: E=Sophos;i="5.99,206,1677571200"; d="scan'208";a="333933319" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2023 03:10:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10683"; a="691050745" X-IronPort-AV: E=Sophos;i="5.99,206,1677571200"; d="scan'208";a="691050745" Received: from ideak-desk.fi.intel.com ([10.237.72.58]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2023 03:10:42 -0700 Date: Tue, 18 Apr 2023 13:10:39 +0300 From: Imre Deak To: Suraj Kandpal Message-ID: References: <20230403080154.1239873-1-suraj.kandpal@intel.com> <20230418092346.1279064-1-suraj.kandpal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230418092346.1279064-1-suraj.kandpal@intel.com> Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/display: Increase AUX timeout for Type-C X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: imre.deak@intel.com Cc: Jani Nikula , intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Apr 18, 2023 at 02:53:46PM +0530, Suraj Kandpal wrote: > Type-C PHYs are taking longer than expected for Aux IO Power Enabling. > Workaround: Increase the timeout. > > WA_14017248603: adlp > Bspec: 55480 > > ---v2 > -change style on how we mention WA [Ankit] > -fix bat error by creating new func that is only called for aux power > well scenarios so we can avoid null pointer error as it is called > everywhere. > > --v3 > -Add non-default enable_timeout to power well descriptor which avoids > adding more platform checks [Imre] > > Cc: Jani Nikula > Cc: Imre Deak > Signed-off-by: Suraj Kandpal > --- > drivers/gpu/drm/i915/display/intel_display_power_map.c | 9 +++++++++ > drivers/gpu/drm/i915/display/intel_display_power_well.c | 3 ++- > drivers/gpu/drm/i915/display/intel_display_power_well.h | 2 ++ > 3 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c > index 6645eb1911d8..4b559de6d036 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c > @@ -1385,6 +1385,15 @@ static const struct i915_power_well_desc xelpd_power_wells_main[] = { > ), > .ops = &icl_aux_power_well_ops, > .fixed_enable_delay = true, > + }, { > + .instances = &I915_PW_INSTANCES( > + I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), > + I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), > + I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3), > + I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4), > + ), > + .ops = &icl_aux_power_well_ops, > + .enable_timeout = true, This should be the duration in ms. Also .fixed_enable_delay = true is needed here as well, as DG2 is a display 13 platform and uses TC1 requiring just waiting a fixed amount of time instead of the regular polling (I forgot to mention this in my previous feedback). > }, { > .instances = &I915_PW_INSTANCES( > I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1), > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c > index 62bafcbc7937..930a42c825c3 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c > @@ -253,6 +253,7 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, > { > const struct i915_power_well_regs *regs = power_well->desc->ops->regs; > int pw_idx = i915_power_well_instance(power_well)->hsw.idx; > + int timeout = power_well->desc->enable_timeout ? : 1; > > /* > * For some power wells we're not supposed to watch the status bit for > @@ -266,7 +267,7 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, > > /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ > if (intel_de_wait_for_set(dev_priv, regs->driver, > - HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) { > + HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) { > drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n", > intel_power_well_name(power_well)); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h > index ba7cb977e7c7..e494df379e6c 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h > @@ -110,6 +110,8 @@ struct i915_power_well_desc { > * Thunderbolt mode. > */ > u16 is_tc_tbt:1; > + /* Enable timeout if greater than the default 1ms */ > + u16 enable_timeout; > }; > > struct i915_power_well { > -- > 2.25.1 >