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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?dRq+uPGmcKsd7IH1vQSBBDl8i1r+28THD2eiNoFTLIsgPV0OmkYRamPB+1W7?= =?us-ascii?Q?ixpqULdBPL4PBQAkaq5xJBkGjPbMi+7bYjQQLlMjbd5Bk8zk3zWYdMryvm9m?= =?us-ascii?Q?JaMAK4wiQCkQPcm5GceEHcz88VSBeQrTIiXHmYtoJkzpYMP84WtvPnsn81u7?= =?us-ascii?Q?E5UkEHwRyseMi+eQBxrN0y/gQjLfGFwIs0amluIpuM9dKuiv0HwHkKflVv+j?= =?us-ascii?Q?kXyeYvx6HS0NhOymXlZhHUWb218+mHTJxNyLDKHbyZ+k8KIDq1D5aBhiVmyD?= =?us-ascii?Q?eWaHSUTUYdqxYBo/6Zr8TZg6gW+6o94P13vafosR+WCmtbbIGpchJ9VRSXYh?= =?us-ascii?Q?U8iEcCF54A7BDL7i0SVieicnxoa7ym9ZcZQELT4aATBY5vletzxTX7IHK2/r?= =?us-ascii?Q?aH/txu/31XqppoTqbF0TtUSfaObgKzrC+zMoVKJQ+ZX4F5x36CpSMJ1lW3/x?= =?us-ascii?Q?lNoChGiJoIABzIEqlQ8kS5Om3qRmfdj3eV6TSSRHKlms3Gg5bRYQAIBmK2qz?= =?us-ascii?Q?IrCXREtH6u+to9VkpCHjBcPbLwFRZl6xyhjSiJYj4MttWvx9lbJABv5rBWYo?= =?us-ascii?Q?nfVGTlARIYG7qCGn/Nj2HCo2WwB0CaVlE0yTYtkzMQ2CHmmuen0TmsqIL+Ka?= =?us-ascii?Q?uwxg/UDiOsxRHpDCXuUF+rBU4FymOx9jcXGwLGF9v6RSXZyvfIm06oa7R4u5?= =?us-ascii?Q?G0ryPankAs4YSWfcT+oCwHhwYQaVGmyAZkNZ3cZya0UKe049Mz0uzmOyYITt?= =?us-ascii?Q?gHRC0e5mkpDZur7+4dhiyaKPe2+S0LLCfsuxhbCNAMmD4EcedpSdDQsRzz79?= =?us-ascii?Q?LUjjORt6jzzaH3kw2sLfvisGqGqyxu7SsIgwsQwEzrMbqitcAizS1suBkxPQ?= =?us-ascii?Q?lPh4ux5jQG71uk2xrm9RptKR4876OwP221Gc6EIUxYdGiWvcbjACbrGe1E1H?= =?us-ascii?Q?RZx8nyHMmNGZbfS8nbSC3I6UWLKjYrFaGuUQorYygd22Pmx7MnBhIO+izkw0?= =?us-ascii?Q?uykp0jJ/nntjmgN+i+1H6DC3LUq518NiQRZnUxhGuQ+nfIKsjaGuZLBoUGky?= =?us-ascii?Q?QngW96Iz0NYaE9QF2mVhukKfkwk0nu/rb4L0V7Y9MeWKD6ZA0enW2YfxHYxf?= =?us-ascii?Q?+a36ZVtJNFOa3KKXjbagzTMEvy6xYzMNienwg1shElclwp0cVajLr9ZCPMGZ?= =?us-ascii?Q?3eSZI+HJSSNayfNvrv+jtfhK8YiI0K9PK/TK8Z4Dnfcs8rgD3vRubXujEvg0?= =?us-ascii?Q?zKYDrAz/qMWJ/DSMF+ecdG47vFIQXICr0VGdRTuWjHWGEty7x1niX+uzr8UI?= =?us-ascii?Q?sD5JCMvRsJh5mE45OFNIOdb3NOQARkAuVoEeJeflE3oou4HyqlnCyRolx61a?= =?us-ascii?Q?YU5bwyRAk4GLbo3M8mLTx4Go0ro4EE8Q7V+jpqKdIdZSUyRwNhXqKDe1lvcM?= =?us-ascii?Q?CITl4E6Y/steAvwuQatevm3lDmAuHw/iKsVv9QFX674u+ec42IPAWVeDdzYv?= =?us-ascii?Q?443NiByi7romMK2AeA+XFr0Lh6kFmkyJTIhBAw37e19v57CJA7EmMFPlUYUL?= =?us-ascii?Q?Xs8mepVOABWtmcdBYTEyLb01Q1q3D77jSsEHZBONUCoUtXPyyqOwzTrGYj6W?= =?us-ascii?Q?YhZYbo2zZW+Ug4xIWtrtVwI=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 0629b8c5-6e49-478d-30a5-08db45c09de4 X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB5971.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2023 19:09:39.6397 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6abe9NvbuZ9+7AEfoK6kGjNZYh8sRB5wvnR/6zSUJTzpHZqqQXPzHy6Dld+3H33RmnAQRQAhk+KHnf4lD+eYgz4K9TgBgaF7kuYZYJCIzfg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR11MB8147 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH 04/13] drm/i915/mtl: C20 port clock calculation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Apr 20, 2023 at 03:40:41PM +0300, Mika Kahola wrote: > Calculate port clock with C20 phy. > > BSpec: 64568 > Signed-off-by: Mika Kahola > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 45 +++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 + > .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++ > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +- > drivers/gpu/drm/i915/display/intel_dpll.c | 2 + > 5 files changed, 55 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 144474540ef4..f7720acaf58c 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2274,6 +2274,51 @@ int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, > return tmpclk; > } > > +int intel_c20pll_calc_port_clock(struct intel_encoder *encoder, > + const struct intel_c20pll_state *pll_state) > +{ > + unsigned int frac, frac_en, frac_quot, frac_rem, frac_den; > + unsigned int multiplier, refclk = 38400; > + unsigned int tx_clk_div; > + unsigned int ref_clk_mpllb_div; > + unsigned int fb_clk_div4_en; > + unsigned int ref, vco; > + unsigned int tx_rate_mult; > + unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); > + > + if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { This method of judging mplla vs mpllb seems more appropriate than the one used during intel_c20pll_readout_hw_state in patch 02/13. Update 2/13 mplla vs mpllb selection based on this logic. Reviewed-by: Radhakrishna Sripada > + tx_rate_mult = 1; > + frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); > + frac_quot = pll_state->mpllb[8]; > + frac_rem = pll_state->mpllb[9]; > + frac_den = pll_state->mpllb[7]; > + multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); > + tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); > + ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); > + fb_clk_div4_en = 0; > + } else { > + tx_rate_mult = 2; > + frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); > + frac_quot = pll_state->mplla[8]; > + frac_rem = pll_state->mplla[9]; > + frac_den = pll_state->mplla[7]; > + multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); > + tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); > + ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); > + fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); > + } > + > + if (frac_en) > + frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den); > + else > + frac = 0; > + > + ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div); > + vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10); > + > + return vco << tx_rate_mult >> tx_clk_div >> tx_rate; > +} > + > static void intel_program_port_clock_ctl(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > bool lane_reversal) > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h > index c643aae27bac..83bd3500091b 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h > @@ -34,6 +34,8 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, > struct intel_c20pll_state *pll_state); > void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, > const struct intel_c20pll_state *hw_state); > +int intel_c20pll_calc_port_clock(struct intel_encoder *encoder, > + const struct intel_c20pll_state *pll_state); > void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state); > int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock); > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > index 6fcb1680fb54..a5e5bee24533 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > @@ -195,17 +195,21 @@ > #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02 > #define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx)) > #define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx)) > +#define C20_PHY_TX_RATE REG_GENMASK(2, 0) > #define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx)) > #define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx)) > #define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx)) > #define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx)) > #define C20_MPLLA_FRACEN REG_BIT(14) > +#define C20_FB_CLK_DIV4_EN REG_BIT(13) > #define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8) > #define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx)) > #define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx)) > #define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13) > #define C20_MPLLB_FRACEN REG_BIT(13) > +#define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10) > #define C20_MULTIPLIER_MASK REG_GENMASK(11, 0) > +#define C20_PHY_USE_MPLLB REG_BIT(7) > > #define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx)) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index d414dd8c26bf..8e6d6afca400 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3856,13 +3856,13 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder, > if (intel_is_c10phy(i915, phy)) { > intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10); > intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10); > + crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10); > } else { > intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20); > intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20); > + crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20); > } > > - crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10); > - > intel_ddi_get_config(encoder, crtc_state); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c > index a9fbef0fa817..ca0f362a40e3 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c > @@ -1014,6 +1014,8 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state, > /* TODO: Do the readback via intel_compute_shared_dplls() */ > if (intel_is_c10phy(i915, phy)) > crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10); > + else > + crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20); > > crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); > > -- > 2.34.1 >