From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85094C77B73 for ; Tue, 30 May 2023 21:05:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D52BA10E428; Tue, 30 May 2023 21:05:51 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 38C7310E431 for ; Tue, 30 May 2023 21:05:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685480749; x=1717016749; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=jmPe0G5tFF61577OT7698lk2qdRVaxrY+8Zsa6BK+M8=; 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charset=us-ascii Content-Disposition: inline In-Reply-To: <20230517132230.1102553-1-tejas.upadhyay@intel.com> Subject: Re: [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi Tejas, On Wed, May 17, 2023 at 06:52:30PM +0530, Tejas Upadhyay wrote: > Wa_14016712196 implementation for mtl > > Bspec: 72197 > > V2: > - Fix kernel test robot warnings > > Reported-by: kernel test robot > Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@intel.com/ > Signed-off-by: Tejas Upadhyay > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 41 ++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index e1c76e5bfa82..737eb515544b 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -177,14 +177,38 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv > return cs; > } > > +static int mtl_dummy_pipe_control(struct i915_request *rq, u32 *cs) > +{ > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + cs = gen12_emit_pipe_control(cs, > + 0, > + PIPE_CONTROL_DEPTH_CACHE_FLUSH, > + LRC_PPHWSP_SCRATCH_ADDR); > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > { > struct intel_engine_cs *engine = rq->engine; > + int err; > > if (mode & EMIT_FLUSH) { > u32 flags = 0; > u32 *cs; > > + /* Wa_14016712196 */ > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) || > + IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0, STEP_B0)) { > + /* dummy PIPE_CONTROL + depth flush */ > + cs = intel_ring_begin(rq, 6); > + err = mtl_dummy_pipe_control(rq, cs); > + if (err) > + return err; > + } > + > flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; > flags |= PIPE_CONTROL_FLUSH_L3; > flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > @@ -218,6 +242,16 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > u32 flags = 0; > u32 *cs, count; > > + /* Wa_14016712196 */ > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) || > + IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0, STEP_B0)) { > + /* dummy PIPE_CONTROL + depth flush */ > + cs = intel_ring_begin(rq, 6); > + err = mtl_dummy_pipe_control(rq, cs); > + if (err) > + return err; > + } > + as the two blocks are basically identical, why not put both of them inside mtl_dummy_pipe_control() and you would basically have something like: /* Wa_14016712196 */ cs = mtl_dummy_pipe_control(rq, cs); if (IS_ERR(cs)) return PTR_ERR(cs); Besides, you check the err value from intel_ring_begin inside mtl_dummy_pipe_control(), which looks a bit weird to me. I'm wondering, though, if we can put both dummy pipe and real pipe in the same command and advance the ring only once at the end... nevermind. Andi