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Mon, 02 Oct 2023 09:55:09 +0300 Date: Mon, 2 Oct 2023 09:55:09 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: "Govindapillai, Vinod" Message-ID: References: <20230914113854.10008-1-ville.syrjala@linux.intel.com> <20230914113854.10008-3-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Patchwork-Hint: comment Subject: Re: [Intel-gfx] [PATCH 3/5] drm/i915/fbc: Split plane tiling checks per-platform X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "intel-gfx@lists.freedesktop.org" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Sun, Oct 01, 2023 at 11:00:44AM +0000, Govindapillai, Vinod wrote: > Hi Ville, > > On Thu, 2023-09-14 at 14:38 +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Carve up tiling_is_valid() into per-platform variants to > > make it easier to see what limits are actually being imposed. > > > > TODO: maybe go for vfuncs later > > > > Signed-off-by: Ville Syrjälä > > --- > >  drivers/gpu/drm/i915/display/intel_fbc.c | 21 ++++++++++++++++++--- > >  1 file changed, 18 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > > index 4c4626c84666..052f9d8b53d4 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > @@ -984,16 +984,21 @@ static bool intel_fbc_hw_tracking_covers_screen(const struct > > intel_plane_state * > >         return effective_w <= max_w && effective_h <= max_h; > >  } > >   > > -static bool tiling_is_valid(const struct intel_plane_state *plane_state) > > +static bool i8xx_fbc_tiling_valid(const struct intel_plane_state *plane_state) > > +{ > > +       const struct drm_framebuffer *fb = plane_state->hw.fb; > > + > > +       return fb->modifier == I915_FORMAT_MOD_X_TILED; > > +} > > + > > +static bool skl_fbc_tiling_valid(const struct intel_plane_state *plane_state) > >  { > > -       struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); > >         const struct drm_framebuffer *fb = plane_state->hw.fb; > >   > >         switch (fb->modifier) { > >         case DRM_FORMAT_MOD_LINEAR: > >         case I915_FORMAT_MOD_Y_TILED: > >         case I915_FORMAT_MOD_Yf_TILED: > > -               return DISPLAY_VER(i915) >= 9; > >         case I915_FORMAT_MOD_4_TILED: > >         case I915_FORMAT_MOD_X_TILED: > >                 return true; > > @@ -1002,6 +1007,16 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state) > >         } > >  } > >   > > +static bool tiling_is_valid(const struct intel_plane_state *plane_state) > > +{ > > +       struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); > > + > > +       if (DISPLAY_VER(i915) >= 9) > > +               return skl_fbc_tiling_valid(plane_state); > > +       else > > +               return i8xx_fbc_tiling_valid(plane_state); > I915_FORMAT_MOD_4_TILED is not checked for i8xx_fbc_tiling_valid() comparing to the original code. > Is that intentional? Tile4 was introduced in dg2/mtl > > With that checked, > > Reviewed-by: Vinod Govindapillai > > > > +} > > + > >  static void intel_fbc_update_state(struct intel_atomic_state *state, > >                                    struct intel_crtc *crtc, > >                                    struct intel_plane *plane) > -- Ville Syrjälä Intel