From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 327C9C07545 for ; Tue, 24 Oct 2023 17:27:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 978DF10E430; Tue, 24 Oct 2023 17:27:44 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4730810E430 for ; Tue, 24 Oct 2023 17:27:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698168463; x=1729704463; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=HSS/Av7nSK7exmv0H+kDtsfbBxeE+oRja17c2ZeUbM0=; b=dnVqkbtHna52l/rsSBndX29fAxCNmx5i6EtyWP9UzxQeL0X7KlPKptp+ nWGQds4hMTm3tlUJoExDFXtAO39zlfGVshkREc55bq1ZeOXdT0F10Mhaw pEV09wYNtyMAu5EdSJdORfwla5ABK1VtrEaR16EuO1XGaieYuNE5Uvixw hnkR3cWDq1ooO1DYD8Yl6BEdyVSdUr9jOFlRg5+99g0UQyCfM6w0we7vp 3cSqrtQIkJueCOmEQoC8jrQjQ04/6SZiEmhne2b2FyOOKlOLgO+vzP6+u qn0EC6zQ3uLRnLv6SUeMyCt/IDlLLi9DzIyiHKnxU+b/ftaSSRdnHYK34 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10873"; a="372180629" X-IronPort-AV: E=Sophos;i="6.03,248,1694761200"; d="scan'208";a="372180629" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 10:27:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10873"; a="882186592" X-IronPort-AV: E=Sophos;i="6.03,248,1694761200"; d="scan'208";a="882186592" Received: from unknown (HELO intel.com) ([10.237.72.65]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 10:27:17 -0700 Date: Tue, 24 Oct 2023 20:27:14 +0300 From: "Lisovskiy, Stanislav" To: Imre Deak Message-ID: References: <20231024010925.3949910-1-imre.deak@intel.com> <20231024010925.3949910-10-imre.deak@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231024010925.3949910-10-imre.deak@intel.com> Subject: Re: [Intel-gfx] [PATCH 09/29] drm/i915/dp_mst: Enable FEC early once it's known DSC is needed X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Oct 24, 2023 at 04:09:05AM +0300, Imre Deak wrote: > Enable FEC in crtc_state, as soon as it's known it will be needed by > DSC. This fixes the calculation of BW allocation overhead, in case DSC > is enabled by falling back to it during the encoder compute config > phase (vs. enabling FEC due to DSC being enabled on other streams). > > Signed-off-by: Imre Deak Reviewed-by: Stanislav Lisovskiy > --- > drivers/gpu/drm/i915/display/intel_dp.c | 6 +++--- > drivers/gpu/drm/i915/display/intel_dp.h | 5 +++++ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +++++++ > 3 files changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 1891c0cc187d1..2048649b420b2 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1369,9 +1369,9 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, > return false; > } > > -static bool intel_dp_supports_fec(struct intel_dp *intel_dp, > - const struct intel_connector *connector, > - const struct intel_crtc_state *pipe_config) > +bool intel_dp_supports_fec(struct intel_dp *intel_dp, > + const struct intel_connector *connector, > + const struct intel_crtc_state *pipe_config) > { > return intel_dp_source_supports_fec(intel_dp, pipe_config) && > drm_dp_sink_supports_fec(connector->dp.fec_capability); > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h > index 484aea215a251..0258580a6aadc 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -137,6 +137,11 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count) > } > > u32 intel_dp_mode_to_fec_clock(u32 mode_clock); > + > +bool intel_dp_supports_fec(struct intel_dp *intel_dp, > + const struct intel_connector *connector, > + const struct intel_crtc_state *pipe_config); > + > u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp); > > void intel_ddi_update_pipe(struct intel_atomic_state *state, > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 80b3df6d51fc8..98d775d862ac4 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -338,6 +338,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); > struct intel_dp *intel_dp = &intel_mst->primary->dp; > + const struct intel_connector *connector = > + to_intel_connector(conn_state->connector); > const struct drm_display_mode *adjusted_mode = > &pipe_config->hw.adjusted_mode; > struct link_config_limits limits; > @@ -380,6 +382,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, > &limits)) > return -EINVAL; > > + if (!intel_dp_supports_fec(intel_dp, connector, pipe_config)) > + return -EINVAL; > + > + pipe_config->fec_enable = !intel_dp_is_uhbr(pipe_config); > + > /* > * FIXME: As bpc is hardcoded to 8, as mentioned above, > * WARN and ignore the debug flag force_dsc_bpc for now. > -- > 2.39.2 >