From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE1D6C4332F for ; Fri, 15 Dec 2023 08:53:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A77310E208; Fri, 15 Dec 2023 08:53:28 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id CBF1510E208 for ; Fri, 15 Dec 2023 08:53:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702630407; x=1734166407; h=date:from:to:cc:subject:message-id:reply-to:references: mime-version:in-reply-to; bh=YhswJf2We8EGO9vXpBgjxhoE/b4yWd8qbV2Kgcm3lY0=; b=TSEDyYQ4yNQOR1xPJQ7xml+FkjO3tt8SIWoxq6ntFS9r80uC7TTXzO5T dSnfGqEGB0M1mKerE9dSZmptVIdqfPmPTVPly+fVGyKLVoWcNI/+xy9hC ppzdG2gvNYgX7JrY4HmiAZTrvXj2g4MpecLqhQkJrUrX6260KUn7g6Dyx 4Bv9FZAqBZvd2fcU5CiOVFsg5dhfZwILcmW1FLatcjyn74JMvMAE3Mssq m7xj0n1JhqiGmx1ofcUamoeVXUvf9UBo0SUfMU/N++Dpos6km7hIZQpG3 3whDmjtbLy0apu3hSGTp3iX9EnxOTs4/NfqoG4Q5+etNd4mTJqJvuj4Xc A==; X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="2102723" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="2102723" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 00:53:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="865339680" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="865339680" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 00:53:25 -0800 Date: Fri, 15 Dec 2023 10:53:31 +0200 From: Imre Deak To: Mika Kahola Subject: Re: [PATCH] drm/i915/display: C20 clock state verification Message-ID: References: <20231215080057.663792-1-mika.kahola@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231215080057.663792-1-mika.kahola@intel.com> X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: imre.deak@intel.com Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Dec 15, 2023 at 10:00:57AM +0200, Mika Kahola wrote: > Add clock state verification for C20. Since we > are usign either A or B contexts, which are > selected based on clock rate, we first need to > calculate hw clock and use that clock to select > which context we are using. Could the description be clearer that the patch _fixes_ the context selection? (Also the subject line should always say _what_ the patch does.) > > Signed-off-by: Mika Kahola > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 775c1c4a8978..6757e9f941e4 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -3079,8 +3079,9 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state, > const struct intel_c20pll_state *mpll_sw_state = &state->cx0pll_state.c20; > bool use_mplla; > int i; > + int hw_clock = intel_c20pll_calc_port_clock(encoder, mpll_hw_state); > > - use_mplla = intel_c20_use_mplla(mpll_hw_state->clock); > + use_mplla = intel_c20_use_mplla(hw_clock); It's mpll_hw_state->tx[0] C20_PHY_USE_MPLLB which tells the HW which context to use, so I think it's better to use the same condition here. > if (use_mplla) { > for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) { > I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i], > @@ -3110,6 +3111,11 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state, > crtc->base.base.id, crtc->base.name, i, > mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]); > } > + > + I915_STATE_WARN(i915, hw_clock != mpll_sw_state->clock, > + "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)", > + crtc->base.base.id, crtc->base.name, > + mpll_sw_state->clock, hw_clock); I think the intel_crtc_state::port_clock SW/HW state verification is equivalent to the above, but it's good to verify it here as well. I would store hw_clock to mpll_hw_state->clock in intel_c20pll_readout_hw_state() though. > } > > void intel_cx0pll_state_verify(struct intel_atomic_state *state, > -- > 2.34.1 >