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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: <intel-gfx@lists.freedesktop.org>, <lucas.demarchi@intel.com>
Subject: Re: [PATCH 4/5] drm/i915: simplify ULT/ULX subplatform detection
Date: Wed, 8 May 2024 09:52:44 -0400	[thread overview]
Message-ID: <ZjuDrK35A9VHNjtd@intel.com> (raw)
In-Reply-To: <87bk5gjw3f.fsf@intel.com>

On Wed, May 08, 2024 at 04:01:56PM +0300, Jani Nikula wrote:
> On Wed, 08 May 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > On Tue, May 07, 2024 at 03:56:51PM +0300, Jani Nikula wrote:
> >> For HSW/BDW ULX machines are also considered ULT. For the sake of
> >> simplicity and clarity, handle this at the IS_XXX_ULT() macro level
> >> instead of two simultaneous subplatforms.
> >> 
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_drv.h          | 9 ++++++---
> >>  drivers/gpu/drm/i915/intel_device_info.c | 4 ----
> >>  2 files changed, 6 insertions(+), 7 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index d1d21d433766..9c57af484ba8 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -562,19 +562,22 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >>  	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
> >>  #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
> >>  				    (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
> >> +/* BDW ULX machines are also considered ULT. */
> >>  #define IS_BROADWELL_ULT(i915) \
> >> -	IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
> >> +	(IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) || \
> >> +	 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX))
> >>  #define IS_BROADWELL_ULX(i915) \
> >>  	IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
> >>  #define IS_BROADWELL_GT3(i915)	(IS_BROADWELL(i915) && \
> >>  				 INTEL_INFO(i915)->gt == 3)
> >> +/* HSW ULX machines are also considered ULT. */
> >>  #define IS_HASWELL_ULT(i915) \
> >> -	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
> >> +	(IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) ||	\
> >> +	 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX))
> >>  #define IS_HASWELL_GT3(i915)	(IS_HASWELL(i915) && \
> >>  				 INTEL_INFO(i915)->gt == 3)
> >>  #define IS_HASWELL_GT1(i915)	(IS_HASWELL(i915) && \
> >>  				 INTEL_INFO(i915)->gt == 1)
> >> -/* ULX machines are also considered ULT. */
> >>  #define IS_HASWELL_ULX(i915) \
> >>  	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
> >>  #define IS_SKYLAKE_ULT(i915) \
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> >> index 27b4a5882be3..a72efa919602 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.c
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> >> @@ -232,10 +232,6 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> >>  	} else if (find_devid(devid, subplatform_ulx_ids,
> >>  			      ARRAY_SIZE(subplatform_ulx_ids))) {
> >>  		mask = BIT(INTEL_SUBPLATFORM_ULX);
> >> -		if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> >> -			/* ULX machines are also considered ULT. */
> >> -			mask |= BIT(INTEL_SUBPLATFORM_ULT);
> >> -		}
> >
> > Oh... it is a long time since I don't look to these bits,
> > but I don't believe that the define above would cover this case here.
> >
> > It seems that you will miss the bits in this platform_mask.
> 
> How come?
> 
> What this does is make ULX platforms also match the ULT checks. Thus I'm
> changing the ULT macros to include ULX subplatforms.
> 
> Or I don't understand what you mean.

I'm sorry, I had missed that mostly that platform_mask is used
at the decision of the defines above.

However, this change would have some side effect:

	err_printf(m, "Subplatform: 0x%x\n",
                   intel_subplatform(&error->runtime_info,
                                     error->device_info.platform));

The signature for GPU hangs error states would change on these
platforms. That could cause some confusion on people debugging
some issues. Although that's so old that I honestly doubt that
it would have some meangninful impact.

up to you:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> BR,
> Jani.
> 
> 
> 
> 
> >
> >>  	} else if (find_devid(devid, subplatform_portf_ids,
> >>  			      ARRAY_SIZE(subplatform_portf_ids))) {
> >>  		mask = BIT(INTEL_SUBPLATFORM_PORTF);
> >> -- 
> >> 2.39.2
> >> 
> 
> -- 
> Jani Nikula, Intel

  reply	other threads:[~2024-05-08 13:52 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-07 12:56 [PATCH 0/5] drm/i915: PCI ID macro and subplatform changes Jani Nikula
2024-05-07 12:56 ` [PATCH 1/5] drm/i915: don't include CML PCI IDs in CFL Jani Nikula
2024-05-07 13:47   ` Rodrigo Vivi
2024-05-08  8:33     ` Jani Nikula
2024-05-08 12:38       ` Rodrigo Vivi
2024-05-08 10:57     ` Ville Syrjälä
2024-05-08 11:45       ` Jani Nikula
2024-05-08 12:01         ` Ville Syrjälä
2024-05-10 10:24           ` Jani Nikula
2024-05-10 10:34             ` Ville Syrjälä
2024-05-10 11:24               ` Jani Nikula
2024-05-07 12:56 ` [PATCH 2/5] drm/i915: don't include RPL-U PCI IDs in RPL-P Jani Nikula
2024-05-08 12:41   ` Rodrigo Vivi
2024-05-07 12:56 ` [PATCH 3/5] drm/i915: separate RPL-U from RPL-P Jani Nikula
2024-05-08 12:46   ` Rodrigo Vivi
2024-05-07 12:56 ` [PATCH 4/5] drm/i915: simplify ULT/ULX subplatform detection Jani Nikula
2024-05-08 12:51   ` Rodrigo Vivi
2024-05-08 13:01     ` Jani Nikula
2024-05-08 13:52       ` Rodrigo Vivi [this message]
2024-05-07 12:56 ` [PATCH 5/5] drm/i915: make the PCI ID macros more flexible Jani Nikula
2024-05-07 13:56 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: PCI ID macro and subplatform changes Patchwork
2024-05-07 13:56 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-07 14:13 ` ✗ Fi.CI.BAT: failure " Patchwork

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