From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C99A0C25B79 for ; Thu, 23 May 2024 13:26:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BE8CE10E501; Thu, 23 May 2024 13:26:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="j7w4eiV9"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3FEBF10E501 for ; Thu, 23 May 2024 13:26:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716470813; x=1748006813; h=date:from:to:cc:subject:message-id:reply-to:references: mime-version:content-transfer-encoding:in-reply-to; bh=qgMuCE/GSLHDJJEkW3DSaEBjUs47LsZCYuTQ7lRsxCY=; b=j7w4eiV9Pp5Q24KALvhdoRjZIAF8i1UZDYTGeAGRfz6Gp3aBDXU08Uqe HRFPWQYE+fG7wPIoArpGJin6YEQc+Dicwjbto1a6ZaGiZbPX0fsWOnyO/ wHCyPJvAH60ocABVriKgHIdjinydf+mkYyq3GT76vh8/yO0+t9yHTMI8W MTlD3CefjYSZebSWdVSgkpdY79BV76vPQsgwqtMNSLXK/jMfmenID36yb /E/pHfOIlIWHld3JvtVbVIAcWcOagwX9bYbWm8yhwsdVafip+Cn1ifjGh nwtX0AmhZBYZR1MuA/AIAkzqn1w3qNwfSUgMdMyXlASfQNPfW8Uf/ZcPY g==; X-CSE-ConnectionGUID: TAwFWASqQdegUgYB3UEPLA== X-CSE-MsgGUID: q5pjFl89T2a4rtVHcJckdg== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="13017556" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="13017556" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:26:52 -0700 X-CSE-ConnectionGUID: U+/zBEOwSl2HZEthmeLE/g== X-CSE-MsgGUID: hLIr4+nqSOGntuI/74P2xA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33679639" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:26:51 -0700 Date: Thu, 23 May 2024 16:26:55 +0300 From: Imre Deak To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org Subject: Re: [PATCH v2 06/21] drm/i915/dp: Use a commit modeset for link retraining MST links Message-ID: References: <20240520185822.3725844-1-imre.deak@intel.com> <20240520185822.3725844-7-imre.deak@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: imre.deak@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, May 23, 2024 at 03:58:30PM +0300, Ville Syrjälä wrote: > On Mon, May 20, 2024 at 09:58:04PM +0300, Imre Deak wrote: > > Instead of direct calls to the link train functions, retrain the link > > via a commit modeset. The direct call means that the output port will be > > disabled/re-enabled while the rest of the pipeline (transcoder) is > > active, which doesn't seem to work on MST at least. It leads to > > underruns and black screen, presumedly because the transcoder is not > > disabled/re-enabled along the port. > > > > Leave switching to a commit modeset on SST for a later patchset, as that > > seems to work ok currently (though better to using a commit there too, > > due to the suppressed underruns). > > > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++++++++++------ > > 1 file changed, 19 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > index 81e620dd33bb7..120f7b420807b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5147,6 +5147,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, > > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > struct intel_crtc *crtc; > > u8 pipe_mask; > > + bool mst_output = false; > > nit: maybe move that up one line to maintain a bit more of a steady slope Ok. > > int ret; > > > > if (!intel_dp_is_connected(intel_dp)) > > @@ -5177,6 +5178,11 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, > > const struct intel_crtc_state *crtc_state = > > to_intel_crtc_state(crtc->base.state); > > > > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { > > + mst_output = true; > > + break; > > + } > > I was pondering if we need a bit more care to make sure all > the pipes agree, but I suppose if that wasn't the case > check_digital_port_conflicts() would have a failed at its > job. So this seems fine. Yes, mixed SST/MST CRTCs connected to the same encoder is what you mean I guess. It would have caused a failure elsewhere or make the commit added here fail during atomic check. > Reviewed-by: Ville Syrjälä > > > + > > /* Suppress underruns caused by re-training */ > > intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); > > if (crtc_state->has_pch_encoder) > > @@ -5184,16 +5190,23 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, > > intel_crtc_pch_transcoder(crtc), false); > > } > > > > + /* TODO: use a modeset for SST as well. */ > > + if (mst_output) { > > + ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx); > > + > > + if (ret && ret != -EDEADLK) > > + drm_dbg_kms(&dev_priv->drm, > > + "[ENCODER:%d:%s] link retraining failed: %pe\n", > > + encoder->base.base.id, encoder->base.name, > > + ERR_PTR(ret)); > > + > > + return ret; > > + } > > + > > for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { > > const struct intel_crtc_state *crtc_state = > > to_intel_crtc_state(crtc->base.state); > > > > - /* retrain on the MST master transcoder */ > > - if (DISPLAY_VER(dev_priv) >= 12 && > > - intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && > > - !intel_dp_mst_is_master_trans(crtc_state)) > > - continue; > > - > > intel_dp_check_frl_training(intel_dp); > > intel_dp_pcon_dsc_configure(intel_dp, crtc_state); > > intel_dp_start_link_train(intel_dp, crtc_state); > > -- > > 2.43.3 > > -- > Ville Syrjälä > Intel